公开(公告)号：US20050258901A1

公开(公告)日：2005-11-24

申请号：US11131281

申请日：2005-05-18

Applicant: Haideh Khorramabadi

Inventor： Haideh Khorramabadi

IPC: H01F17/00 ,  H01L23/522 ,  H01L27/02 ,  H01L27/08 ,  H03B1/00 ,  H03B5/12 ,  H03B5/36 ,  H03D7/16 ,  H03D7/18 ,  H03G1/00 ,  H03H11/12 ,  H03J1/00 ,  H03J3/04 ,  H03J3/08 ,  H03J3/18 ,  H03L1/02 ,  H03L7/10 ,  H03L7/23 ,  H03F3/45

CPC classification number: H03L7/23 ,  H01F17/0006 ,  H01F17/0013 ,  H01F2017/0053 ,  H01F2021/125 ,  H01L23/5227 ,  H01L27/0248 ,  H01L27/08 ,  H01L2924/0002 ,  H01L2924/3011 ,  H03B5/1215 ,  H03B5/1228 ,  H03B5/364 ,  H03B2201/025 ,  H03B2201/0266 ,  H03D7/161 ,  H03D7/18 ,  H03F1/3211 ,  H03F1/52 ,  H03F3/191 ,  H03F3/45183 ,  H03F3/45188 ,  H03F3/45475 ,  H03F2200/294 ,  H03F2203/45318 ,  H03F2203/45704 ,  H03G1/0029 ,  H03H11/1291 ,  H03J1/0075 ,  H03J3/04 ,  H03J3/08 ,  H03J3/185 ,  H03J2200/10 ,  H03L1/023 ,  H03L7/10 ,  H03L7/18 ,  H01L2924/00

Abstract: An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit. A receiver front end provides programable attenuation and a programable gain low noise amplifier. LC filters integrated onto the substrate in conjunction with image reject mixers provide image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. Active filters utilize multi track spiral inductors with shields to increase circuit Q. The filters incorporate a gain stage that provides improved dynamic range through the use of cross coupled auxiliary differential pair CMOS amplifiers to cancel distortion in a main linearized differential pair amplifier. Frequency planning provides additional image rejection. Local oscillator signal generation methods on chip reduce distortion. A PLL generates needed out of band LO signals. Direct synthesis generates in band LO signals. PLL VCOs are centered automatically. A differential crystal oscillator provides a frequency reference. Differential signal transmission throughout the receiver is used. ESD protection is provided by a pad ring and ESD clamping structure. Shunts utilize a gate boosting at each pin to discharge ESD build up. An IF VGA utilizes distortion cancellation achieved with cross coupled differential pair amplifiers having their Vds dynamically modified in conjunction with current steering of the differential pairs sources.

Abstract translation: 具有通道选择和图像抑制的集成接收器基本上在单个CMOS集成电路上实现。 接收机前端提供可编程衰减和可编程增益低噪声放大器。 与图像抑制混合器一起集成到衬底上的LC滤波器提供图像频率抑制。 过滤器调谐和电感Q补偿温度在芯片上执行。 有源滤波器利用具有屏蔽的多轨螺旋电感器来增加电路Q.滤波器包括增益级，其通过使用交叉耦合辅助差分对CMOS放大器来消除主线性化差分对放大器中的失真而提供改进的动态范围。 频率规划提供额外的镜像抑制。 本地振荡器信号产生方法在芯片上减少失真。 PLL产生所需的带外LO信号。 直接合成产生带内LO信号。 PLL VCO自动居中。 差分晶体振荡器提供频率参考。 使用整个接收机的差分信号传输。 ESD保护由衬垫环和ESD夹紧结构提供。 分流器利用每个引脚上的门极升压来放电ESD积聚。 IF VGA利用交叉耦合的差分对放大器实现的失真消除，其具有与差分对源的当前转向结合动态修改的V ds。

公开(公告)号：US20050227627A1

公开(公告)日：2005-10-13

申请号：US11055589

申请日：2005-02-10

Applicant: Russell Cyr ,  Geoffrey Dawe

Inventor： Russell Cyr ,  Geoffrey Dawe

IPC: H02M3/24 ,  H03B1/00 ,  H03B5/12 ,  H03C3/22 ,  H03D3/00 ,  H03F1/06 ,  H03F1/08 ,  H03F1/22 ,  H03F1/26 ,  H03F1/32 ,  H03F3/19 ,  H03F3/191 ,  H03F3/195 ,  H03F3/45 ,  H03F3/60 ,  H03G1/00 ,  H03G3/30 ,  H03L7/00 ,  H03L7/099 ,  H03L7/10 ,  H03L7/185 ,  H04B1/00 ,  H04B1/40 ,  H04L12/28 ,  H04L12/56

CPC classification number: H03F1/26 ,  H01L23/66 ,  H01L24/48 ,  H01L24/49 ,  H01L2223/6611 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/484 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/014 ,  H01L2924/12034 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/1461 ,  H01L2924/15153 ,  H01L2924/15157 ,  H01L2924/15165 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/30111 ,  H03B5/1215 ,  H03B5/1228 ,  H03B5/1243 ,  H03B5/1265 ,  H03B5/1293 ,  H03B2201/0208 ,  H03B2201/0266 ,  H03C3/225 ,  H03D3/007 ,  H03F1/0205 ,  H03F1/08 ,  H03F1/223 ,  H03F1/3294 ,  H03F3/191 ,  H03F3/195 ,  H03F3/4521 ,  H03F3/60 ,  H03F2200/111 ,  H03F2200/225 ,  H03F2200/294 ,  H03F2200/331 ,  H03F2200/366 ,  H03F2200/372 ,  H03F2200/391 ,  H03F2200/429 ,  H03F2200/543 ,  H03F2200/78 ,  H03F2203/45256 ,  H03G3/3068 ,  H03J2200/10 ,  H03L7/099 ,  H03L7/10 ,  H03L7/185 ,  H04B1/006 ,  H04B1/40 ,  H04W24/00 ,  H04W80/00 ,  H04W88/02 ,  H01L2924/00011 ,  H01L2224/45099 ,  H01L2924/00

Abstract: A fully integrated, programmable mixed-signal radio transceiver comprising a radio frequency integrated circuit (RFIC) which is frequency and protocol agnostic with digital inputs and outputs, the radio transceiver being programmable and configurable for multiple radio frequency bands and standards and being capable of connecting to many networks and service providers. The RFIC includes a tunable resonant circuit that includes a transmission line having an inductance, a plurality of switchable capacitors configured to be switched into and out of the tunable resonant circuit in response to a first control signal, and at least one variable capacitor that can be varied in response to a second control signal, wherein a center resonant frequency of the resonant circuit is electronically tunable responsive to the first and second control signals that control a first capacitance value of the plurality of switchable capacitors and a second capacitance value of the at least one variable capacitor.

公开(公告)号：US06954113B2

公开(公告)日：2005-10-11

申请号：US10367766

申请日：2003-02-19

Applicant: John W. Fallisgaard ,  Eugene S. Trefethan

Inventor： John W. Fallisgaard ,  Eugene S. Trefethan

IPC: H03B5/32 ,  H03B1/00 ,  H03B5/36 ,  H03B19/00 ,  H03L7/089 ,  H03L7/18 ,  H03L7/183

CPC classification number: H03L7/183 ,  H03B5/366 ,  H03B19/00 ,  H03B2201/0266 ,  H03J2200/10 ,  H03L7/0898

Abstract: A programmable crystal oscillator is provided having a memory for storing frequency-defining parameters. Typically, one of these parameters is used to program an adjustable capacitive load circuit coupled to a crystal to thereby adjust the crystal source frequency. Additional parameters are used to program the output frequency of a phase locked loop circuit coupled to receive the adjusted source frequency. A further parameter can also be used to divide the output frequency of the phase locked loop circuit to supply a specified output frequency. The oscillators can be manufactured as generic programmable crystal oscillators without regard for output frequency and then quickly programmed to produce customer-specified output frequencies with a high degree of accuracy.

Abstract translation: 提供了一种可编程晶体振荡器，其具有用于存储频率定义参数的存储器。 通常，这些参数之一用于对耦合到晶体的可调容性负载电路进行编程，从而调节晶体源频率。 附加参数用于编程耦合以接收经调整的源频率的锁相环电路的输出频率。 还可以使用另外的参数来分频锁相环电路的输出频率以提供指定的输出频率。 振荡器可以制造为通用可编程晶体振荡器，而不考虑输出频率，然后快速编程，以高精度产生客户指定的输出频率。

公开(公告)号：US20050212614A1

公开(公告)日：2005-09-29

申请号：US11043385

申请日：2005-01-25

Applicant: Vincenzo Peluso

Inventor： Vincenzo Peluso

IPC: H03B1/00 ,  H03B5/12 ,  H03B5/00

CPC classification number: H03B5/1228 ,  H03B5/1215 ,  H03B5/1231 ,  H03B5/1243 ,  H03B5/1265 ,  H03B5/1287 ,  H03B5/1293 ,  H03B2201/0266 ,  H03B2201/0283 ,  H03J1/005 ,  H03J2200/10

Abstract: A programmable capacitor bank includes multiple tuning elements. Each tuning element includes two tuning capacitors and a pass transistor that electrically connects or disconnects the capacitors to/from common nodes. For a thermometer decoded capacitor bank, the tuning capacitors for all tuning elements have equal capacitance. Each tuning element further includes at least one pull-up transistor that provides high bias voltage for the pass transistor and at least one pull-down transistor that provides low bias voltage for the pass transistor. The multiple tuning elements may be arranged in a ladder topology such that (1) the tuning elements are turned on in sequential order starting from one end of the ladder and going toward the other end of the ladder and (2) each tuning element receives biasing from a preceding tuning element and provides biasing to a succeeding tuning element. The capacitor bank may be used for VCOs and other circuits.

Abstract translation: 可编程电容器组包括多个调谐元件。 每个调谐元件包括两个调谐电容器和将电容器与公共节点电连接或断开的通过晶体管。 对于温度计解码电容器组，用于所有调谐元件的调谐电容器具有相等的电容。 每个调谐元件还包括提供用于传输晶体管的高偏置电压的至少一个上拉晶体管和为传输晶体管提供低偏置电压的至少一个下拉晶体管。 多个调谐元件可以被布置成梯形拓扑结构，使得（1）调谐元件从梯子的一端开始并且朝着梯子的另一端顺序地接通，并且（2）每个调谐元件接收偏置 并且向后续的调谐元件提供偏置。 电容器组可用于VCO和其他电路。

公开(公告)号：US06861915B2

公开(公告)日：2005-03-01

申请号：US10201467

申请日：2002-07-23

Applicant: Kuichi Kubo ,  Fumio Asamura

Inventor： Kuichi Kubo ,  Fumio Asamura

IPC: H03B5/32 ,  H03B1/00 ,  H03B5/36

CPC classification number: H03B5/368 ,  H03B2201/0266

Abstract: A crystal oscillator has a quartz-crystal unit, a first oscillating capacitor connected between a first end of the crystal unit and a reference potential point, a second oscillating capacitor connected between a second end of the crystal unit and the reference potential point, a CMOS inverter connected parallel to the crystal unit, and a feedback resistor connected across the inverter. The crystal oscillator can easily be incorporated into integrated circuits and has an increased variable oscillation frequency range. The crystal oscillator also has an adjustable capacitive assembly having selectable capacitances which is connected parallel to a combined capacitor comprising the first and the second oscillating capacitors.

Abstract translation: 晶体振荡器具有石英晶体单元，连接在晶体单元的第一端和参考电位点之间的第一振荡电容器，连接在晶体单元的第二端和参考电位点之间的第二振荡电容器，CMOS 逆变器并联到晶体单元，反馈电阻连接在逆变器上。 晶体振荡器可以方便地集成到集成电路中，并且具有增加的可变振荡频率范围。 晶体振荡器还具有可调电容组件，其具有与包括第一和第二振荡电容器的组合电容器并联连接的可选电容。

公开(公告)号：US20040021181A1

公开(公告)日：2004-02-05

申请号：US10631833

申请日：2003-08-01

Inventor： Kaare Tais Christensen

IPC: H01L029/76

CPC classification number: H03J5/244 ,  H01L23/4824 ,  H01L2924/0002 ,  H03B5/1212 ,  H03B5/1231 ,  H03B5/1265 ,  H03B5/1268 ,  H03B5/366 ,  H03B2201/0266 ,  H03J2200/10 ,  H01L2924/00

Abstract: A tuning circuit comprising a first reactance, a second reactance and a insulated gate field effect transistor having a gate arranged to receive a control signal. The first reactance is connected between the source of the field effect transistor and a first node. The second reactance has the same value as the first reactance and is connected between the drain of the field effect transistor and a second node. The first and second nodes are arranged so as to experience a balanced ac signal. Turning the field effect transistor on has the effect of making the first and second reactances effective in the circuit and vice versa.

Abstract translation: 一种包括第一电抗，第二电抗和绝缘栅场效应晶体管的调谐电路，其具有布置成接收控制信号的栅极。 第一电抗连接在场效应晶体管的源极和第一节点之间。 第二电抗具有与第一电抗相同的值，并连接在场效应晶体管的漏极和第二节点之间。 第一和第二节点布置成经历平衡的交流信号。 导通场效应晶体管具有使第一和第二电抗在电路中有效的效果，反之亦然。

公开(公告)号：US06664860B2

公开(公告)日：2003-12-16

申请号：US09754192

申请日：2001-01-05

Applicant: John W. Fallisgaard ,  Eugene S. Trefethan

Inventor： John W. Fallisgaard ,  Eugene S. Trefethan

IPC: H03L700

CPC classification number: H03L7/183 ,  H03B5/366 ,  H03B19/00 ,  H03B2201/0266 ,  H03J2200/10 ,  H03L7/0898

Abstract: A programmable crystal oscillator is provided having a memory for storing frequency-defining parameters. Typically, one of these parameters is used to program an adjustable capacitive load circuit coupled to a crystal to thereby adjust the crystal source frequency. Additional parameters are used to program the output frequency of a phase locked loop circuit coupled to receive the adjusted source frequency. A further parameter can also be used to divide the output frequency of the phase locked loop circuit to supply a specified output frequency. The oscillators can be manufactured as generic programmable crystal oscillators without regard for output frequency and then quickly programmed to produce customer-specified output frequencies with a high degree of accuracy.

Abstract translation: 提供了一种可编程晶体振荡器，其具有用于存储频率定义参数的存储器。 通常，这些参数之一用于对耦合到晶体的可调容性负载电路进行编程，从而调节晶体源频率。 附加参数用于编程耦合以接收经调整的源频率的锁相环电路的输出频率。 还可以使用另外的参数来分频锁相环电路的输出频率以提供指定的输出频率。 振荡器可以制造为通用可编程晶体振荡器，而不考虑输出频率，然后快速编程，以高精度产生客户指定的输出频率。

公开(公告)号：US20030067362A1

公开(公告)日：2003-04-10

申请号：US10268176

申请日：2002-10-10

Inventor： Reinhard Losehand ,  Hubert Werthmann ,  Ulf Bartl

IPC: H03B001/00

CPC classification number: H03J3/20 ,  H03B2201/0266 ,  H03J3/185 ,  H03J2200/10

Abstract: A conductor network includes trimming capacitors and is connected in parallel with a resonant circuit. The trimming capacitors can be connected in parallel with the variable-capacitance diodes in the resonant circuit through PIN diodes, enabling trimming of the resonant circuit.

Abstract translation: 导体网络包括微调电容器并且与谐振电路并联连接。 微调电容器可以通过PIN二极管与谐振电路中的可变电容二极管并联连接，从而能够修整谐振电路。

公开(公告)号：US20030003884A1

公开(公告)日：2003-01-02

申请号：US10183504

申请日：2002-06-28

Inventor： Masanao Fujiwara

IPC: H01Q011/12

CPC classification number: H03B5/32 ,  H03B2201/0266 ,  H04B1/28

Abstract: This invention provides a wireless communication device having high receiving sensitivity and made compact at low cost and having a high general purpose property, and able to transmit and receive information by multiplying the frequencies of plural channels several times and arbitrarily selecting all wireless frequency bands in a predetermined range. A receiving section has one crystal resonator 122, an inductor 124 able to be connected in series to the crystal resonator 122, and a channel change-over switch 123 for switching whether the inductor 124 is connected to the crystal resonator 122 and the ground, or the crystal resonator 122 is directly connected to the ground, and an adjusting change-over switch 125. A transmitting section has one crystal resonator 321, plural frequency setting adjusting circuits 312,313 each including an inductor 314,316 for determining a frequency oscillated from an oscillator, and a switching connection switch 318 for switching and connecting one of the plural frequency setting adjusting circuits 312,313 to a modulating circuit 320 connected to the crystal resonator 321.

Abstract translation: 本发明提供了一种具有高接收灵敏度并且成本低廉并且具有高通用性能的高接收灵敏度的无线通信设备，并且能够通过将多个信道的频率相乘多次来发送和接收信息，并且任意地选择所有无线频带 预定范围。 接收部具有一个晶体谐振器122，能够与晶体谐振器122串联连接的电感器124和用于切换电感器124是否连接到晶体谐振器122和地的通道转换开关123，或者 晶体谐振器122直接连接到地和调整转换开关125.发送部分具有一个晶体谐振器321，多个频率设定调节电路312,313，每个频率设定调节电路312,313包括用于确定从振荡器振荡的频率的电感器314,316，以及 用于将多个频率设定调节电路312,313中的一个切换并连接到连接到晶体谐振器321的调制电路320的开关连接开关318。

公开(公告)号：US06433658B1

公开(公告)日：2002-08-13

申请号：US09542183

申请日：2000-04-04

Applicant: Ali Rastegar

Inventor： Ali Rastegar

IPC: H03J320

CPC classification number: H03F1/56 ,  H03B5/08 ,  H03B2201/0208 ,  H03B2201/025 ,  H03B2201/0266 ,  H03F3/191 ,  H03J1/0008 ,  H03J5/246 ,  H03J2200/10 ,  H03M1/804

Abstract: A structure (110, 150) for enhancing the quality factor (Q) of a capacitive circuit (112, 152). The capacitive circuit (112, 152) includes a first resistance (122, 164), a capacitance (124, 166), and a second resistance (126, 168). The capacitance (124, 166) represents the net capacitance of the capacitive circuit (112, 152), and the first resistance (122, 164) and second resistance (126, 168) represent elements of the intrinsic resistance of the capacitive circuit (112, 152). In a one embodiment the structure (110) includes a first capacitor (128) which is connected in parallel with the capacitive circuit (112), and second capacitor (130) which is connected in series with the capacitive circuit (112). In a second embodiment the structure (150) includes a first inductor (164), connected in series between the capacitive circuit (152) and a node (162) where the first capacitor (174) and one end of the second capacitor (176) connect, and a second inductor (172) connected in series between the capacitive circuit (152) and the other end of the second capacitor (130).

Abstract translation: 一种用于增强电容电路（112,152）的品质因数（Q）的结构（110,150）。 电容电路（112,152）包括第一电阻（122,164），电容（124,166）和第二电阻（126,168）。 电容（124,166）表示电容电路（112,152）的净电容，第一电阻（122,164）和第二电阻（126,168）表示电容电路（112）的固有电阻的元件 ，152）。 在一个实施例中，结构（110）包括与电容电路（112）并联连接的第一电容器（128）和与电容电路（112）串联连接的第二电容器（130）。 在第二实施例中，结构（150）包括串联连接在电容电路（152）和节点（162）之间的第一电感器（164），其中第一电容器（174）和第二电容器（176）的一端 连接，并且串联连接在电容电路（152）和第二电容器（130）的另一端之间的第二电感器（172）。