公开(公告)号：US09960242B2

公开(公告)日：2018-05-01

申请号：US15468541

申请日：2017-03-24

Applicant: Silicon Storage Technology, Inc.

Inventor： Chunming Wang

IPC: H01L29/66 ,  H01L29/423 ,  H01L27/11521

CPC classification number: H01L29/42328 ,  H01L27/11521

Abstract: A reduced size non-volatile memory cell array is achieved by forming first trenches in an insulation layer in the row direction, filling the first trenches with insulation material, forming second trenches in the insulation layer in the column direction, forming the STI isolation material in the second trenches, and forming the source regions through the first trenches. Alternately, the STI isolation regions can be made continuous, and the source diffusion implant has sufficient energy to form continuous source line diffusions that each extend across the active regions and under the STI isolation regions. This allows control gates of adjacent memory cell pairs to be formed closer together.

公开(公告)号：US20180069104A1

公开(公告)日：2018-03-08

申请号：US15474879

申请日：2017-03-30

Applicant: Silicon Storage Technology Inc.

Inventor： Feng Zhou ,  Xian Liu ,  Chien-Sheng Su ,  Nhan Do ,  Chunming Wang

IPC: H01L29/66 ,  H01L29/423

CPC classification number: H01L29/66825 ,  G11C2216/10 ,  H01L21/28273 ,  H01L27/0705 ,  H01L29/0847 ,  H01L29/42328 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/788

Abstract: A simplified method for forming pairs of non-volatile memory cells using two polysilicon depositions. A first polysilicon layer is formed on and insulated from the semiconductor substrate in a first polysilicon deposition process. A pair of spaced apart insulation blocks are formed on the first polysilicon layer. Exposed portions of the first poly silicon layer are removed while maintaining a pair of polysilicon blocks of the first polysilicon layer each disposed under one of the pair of insulation blocks. A second polysilicon layer is formed over the substrate and the pair of insulation blocks in a second polysilicon deposition process. Portions of the second polysilicon layer are removed while maintaining a first polysilicon block (disposed between the pair of insulation blocks), a second polysilicon block (disposed adjacent an outer side of one insulation block), and a third polysilicon block (disposed adjacent an outer side of the other insulation block).

公开(公告)号：US20180040482A1

公开(公告)日：2018-02-08

申请号：US15594883

申请日：2017-05-15

Applicant: Silicon Storage Technology, Inc.

Inventor： Chien-Sheng Su ,  Jeng-Wei Yang ,  Man-Tang Wu ,  Chun-Ming Chen ,  Hieu Van Tran ,  Nhan Do

IPC: H01L21/28 ,  H01L29/423 ,  H01L29/772 ,  H01L21/306 ,  G11C16/04

CPC classification number: H01L21/28 ,  G11C16/0425 ,  H01L21/28273 ,  H01L21/30604 ,  H01L27/11539 ,  H01L29/42328 ,  H01L29/772

Abstract: A method of forming a memory device that includes forming a first insulation layer on a semiconductor substrate, forming a conductive material layer on the first insulation layer, forming an insulation block on the conductive material layer, forming an insulation spacer along a side surface of the insulation block and on the conductive material layer, etching the conductive material layer to form a block of the conductive material disposed directly under the insulation block and the insulation spacer, removing the insulation spacer, forming a second insulation layer having a first portion wrapping around an exposed upper edge of the block of the conductive material and a second portion disposed on a first portion of the first insulation layer over the substrate, and forming a conductive block insulated from the block of the conductive material by the second insulation layer and from the substrate by the first and second insulation layers.

公开(公告)号：US20170337978A1

公开(公告)日：2017-11-23

申请号：US15158460

申请日：2016-05-18

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Anh Ly ,  Thuan Vu

IPC: G11C16/34 ,  G11C16/08 ,  G11C16/16 ,  G11C16/28

CPC classification number: G11C16/3431 ,  G11C16/0425 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16 ,  G11C16/28

Abstract: The present invention relates to a flash memory cell with only four terminals and decoder circuitry for operating an array of such flash memory cells. The invention allows for fewer terminals for each flash memory cell compared to the prior art, which results in a simplification of the decoder circuitry and overall die space required per flash memory cells. The invention also provides for the use of high voltages on one or more of the four terminals to allow for read, erase, and programming operations despite the lower number of terminals compared to prior art flash memory cells.

公开(公告)号：US20170337466A1

公开(公告)日：2017-11-23

申请号：US15594439

申请日：2017-05-12

Applicant: Silicon Storage Technology, Inc. ,  The Regents of the University of California

Inventor： Farnood Merrikh Bayat ,  Xinjie Guo ,  Dmitri Strukov ,  Nhan Do ,  Hieu Van Tran ,  Vipin Tiwari ,  Mark Reiten

IPC: G06N3/04 ,  G06F3/06

CPC classification number: G06N3/04 ,  G06F3/061 ,  G06F3/0655 ,  G06F3/0688 ,  G06N3/0454 ,  G06N3/063

Abstract: An artificial neural network device that utilizes one or more non-volatile memory arrays as the synapses. The synapses are configured to receive inputs and to generate therefrom outputs. Neurons are configured to receive the outputs. The synapses include a plurality of memory cells, wherein each of the memory cells includes spaced apart source and drain regions formed in a semiconductor substrate with a channel region extending there between, a floating gate disposed over and insulated from a first portion of the channel region and a non-floating gate disposed over and insulated from a second portion of the channel region. Each of the plurality of memory cells is configured to store a weight value corresponding to a number of electrons on the floating gate. The plurality of memory cells are configured to multiply the inputs by the stored weight values to generate the outputs.

公开(公告)号：US20170330949A1

公开(公告)日：2017-11-16

申请号：US15468541

申请日：2017-03-24

Applicant: Silicon Storage Technology, Inc.

Inventor： Chunming Wang

IPC: H01L29/423 ,  H01L27/11521

CPC classification number: H01L29/42328 ,  H01L27/11521

Abstract: A reduced size non-volatile memory cell array is achieved by forming first trenches in an insulation layer in the row direction, filling the first trenches with insulation material, forming second trenches in the insulation layer in the column direction, forming the STI isolation material in the second trenches, and forming the source regions through the first trenches. Alternately, the STI isolation regions can be made continuous, and the source diffusion implant has sufficient energy to form continuous source line diffusions that each extend across the active regions and under the STI isolation regions. This allows control gates of adjacent memory cell pairs to be formed closer together.

公开(公告)号：US09747986B2

公开(公告)日：2017-08-29

申请号：US15003811

申请日：2016-01-22

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Hung Quoc Nguyen ,  Anh Ly ,  Thuan Vu

IPC: G06F17/50 ,  G11C16/08 ,  G11C11/16 ,  G11C13/00 ,  G11C16/28

CPC classification number: G11C16/08 ,  G06F17/5081 ,  G11C7/062 ,  G11C8/10 ,  G11C11/1673 ,  G11C13/004 ,  G11C16/26 ,  G11C16/28

Abstract: Improved PMOS and NMOS transistor designs for sensing circuitry use in advanced nanometer flash memory devices are disclosed.

公开(公告)号：US20170148902A1

公开(公告)日：2017-05-25

申请号：US15368451

申请日：2016-12-02

Applicant: Silicon Storage Technology, Inc.

Inventor： Nhan Do

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/423 ,  H01L27/11565 ,  H01L27/11568

CPC classification number: H01L29/66833 ,  H01L21/0217 ,  H01L27/1052 ,  H01L27/11565 ,  H01L27/11568 ,  H01L29/42344 ,  H01L29/42352 ,  H01L29/66825 ,  H01L29/7926

Abstract: A memory cell formed by forming a trench in the surface of a substrate. First and second spaced apart regions are formed in the substrate with a channel region therebetween. The first region is formed under the trench. The channel region includes a first portion that extends along a sidewall of the trench and a second portion that extends along the surface of the substrate. A charge trapping layer in the trench is adjacent to and insulated from the first portion of the channel region for controlling the conduction of the channel region first portion. An electrically conductive gate in the trench is adjacent to and insulated from the charge trapping layer and from the first region and is capacitively coupled to the charge trapping layer. An electrically conductive control gate is disposed over and insulated from the second portion of the channel region for controlling its conduction.

公开(公告)号：US09659946B2

公开(公告)日：2017-05-23

申请号：US15287672

申请日：2016-10-06

Applicant: Silicon Storage Technology, Inc.

Inventor： Chien-Sheng Su ,  Jeng-Wei Yang ,  Yueh-Hsin Chen

IPC: H01L27/11521 ,  H01L29/423 ,  H01L29/66 ,  H01L29/16

CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L21/823425 ,  H01L29/1608 ,  H01L29/42328 ,  H01L29/66825

Abstract: A memory device having a pair of conductive floating gates with inner sidewalls facing each other, and disposed over and insulated from a substrate of first conductivity type. A pair of spaced apart conductive control gates each disposed over and insulated from one of the floating gates, and each including inner sidewalls facing each other. A pair of first spacers of insulation material extending along control gate inner sidewalls and over the floating gates. The floating gate inner sidewalls are aligned with side surfaces of the first spacers. A pair of second spacers of insulation material each extend along one of the first spacers and along one of the floating gate inner sidewalls. A trench formed into the substrate having sidewalls aligned with side surfaces of the second spacers. Silicon carbon disposed in the trench. Material implanted into the silicon carbon forming a first region having a second conductivity type.

公开(公告)号：US20170125429A1

公开(公告)日：2017-05-04

申请号：US15295022

申请日：2016-10-17

Applicant: Silicon Storage Technology, Inc.

Inventor： CHIEN-SHENG SU ,  FENG ZHOU ,  JENG-WEI YANG ,  HIEU VAN TRAN ,  NHAN DO

IPC: H01L27/115 ,  H01L29/423 ,  H01L29/66 ,  H01L21/28 ,  H01L29/788

CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L27/11524 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/788 ,  H01L29/7881

Abstract: A memory device including a silicon substrate having a planar upper surface in a memory cell area and an upwardly extending silicon fin in a logic device area. The silicon fin includes side surfaces extending up and terminating at a top surface. The logic device includes spaced apart source and drain regions with a channel region extending there between (along the top surface and the side surfaces), and a conductive logic gate disposed over the top surface and laterally adjacent to the side surfaces. The memory cell includes spaced apart source and drain regions with a second channel region extending there between, a conductive floating gate disposed over one portion of the second channel region, a conductive word line gate disposed over another portion of the second channel region, a conductive control gate disposed over the floating gate, and a conductive erase gate disposed over the source region.