中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

239 records (took 0.03 seconds)

    Field effect transistor device and fabrication
    182.
    发明授权
    Field effect transistor device and fabrication 有权
    场效应晶体管器件和制造

    公开(公告)号：US08736023B2

    公开(公告)日：2014-05-27

    申请号：US13775369

    申请日：2013-02-25

    Applicant: International Business Machines Corporation

    Inventor： Dechao Guo ,  Shu-Jen Han ,  Chung-Hsun Lin ,  Yanfeng Wang

    IPC: H01L29/772 ,  H01L29/423 ,  H01L29/66 ,  H01L21/8238

    CPC classification number: H01L29/42368 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823871 ,  H01L29/66477

    Abstract: A method for forming a field effect transistor (FET) device includes forming a dielectric layer on a substrate, forming a first metal layer on the dielectric layer, removing a portion of the first metal layer to expose a portion of the dielectric layer, forming a second metal layer on the dielectric layer and the first metal layer, and removing a portion of the first metal layer and the second metal layer to define a boundary region between a first FET device and a second FET device.

    Abstract translation: 一种用于形成场效应晶体管（FET）器件的方法，包括在衬底上形成电介质层，在电介质层上形成第一金属层，去除第一金属层的一部分以露出电介质层的一部分，形成 在所述电介质层和所述第一金属层上的第二金属层，以及去除所述第一金属层和所述第二金属层的一部分，以限定第一FET器件和第二FET器件之间的边界区域。

    Self-Aligned III-V MOSFET Fabrication with In-Situ III-V Epitaxy And In-Situ Metal Epitaxy And Contact Formation
    184.
    发明申请
    Self-Aligned III-V MOSFET Fabrication with In-Situ III-V Epitaxy And In-Situ Metal Epitaxy And Contact Formation 有权
    具有原位III-V外延和原位金属外延和接触形成的自对准III-V MOSFET制造

    公开(公告)号：US20130309830A1

    公开(公告)日：2013-11-21

    申请号：US13950777

    申请日：2013-07-25

    Applicant: International Business Machines Corporation

    Inventor： Dechao Guo ,  Shu-Jen Han ,  Jeehwan Kim ,  Kuen-Ting Shiu

    IPC: H01L29/66

    CPC classification number: H01L29/78 ,  H01L29/0847 ,  H01L29/41783 ,  H01L29/452 ,  H01L29/66477 ,  H01L29/66522 ,  H01L29/66628

    Abstract: A method for forming a transistor includes providing a patterned gate stack disposed on a III-V substrate and having sidewall spacers formed on sides of the patterned gate stack, the III-V substrate including source/drain regions adjacent to the sidewall spacers and field oxide regions formed adjacent to the source/drain regions. The method includes growing raised source/drain regions on the source/drain regions, the grown raised source/drain regions including III-V semiconductor material, and growing metal contacts on the grown raised source/drain regions. Another method for forming a transistor includes providing a patterned gate stack disposed on a III-V substrate and having sidewall spacers formed on sides of the patterned gate stack, the III-V substrate including source/drain regions adjacent to the sidewall spacers and field oxide regions formed adjacent to the source/drain regions. The method includes growing metal contacts on the source/drain regions. Transistors and computer program products are also disclosed.

    Abstract translation: 一种用于形成晶体管的方法，包括提供设置在III-V衬底上的图案化栅极堆叠并且具有形成在图案化栅极叠层的侧面上的侧壁间隔物，III-V衬底包括与侧壁间隔物相邻的源极/漏极区域和场氧化物 与源/漏区相邻形成的区域。 该方法包括在源极/漏极区域上生长凸起的源极/漏极区域，生长的升高的源极/漏极区域包括III-V半导体材料，以及在生长的升高的源极/漏极区域上生长的金属接触。 形成晶体管的另一种方法包括提供设置在III-V衬底上并且具有形成在图案化栅极堆叠的侧面上的侧壁间隔物的图案化栅极堆叠，所述III-V衬底包括与侧壁间隔物相邻的源极/漏极区域和场氧化物 与源/漏区相邻形成的区域。 该方法包括在源/漏区上生长金属接触。 还公开了晶体管和计算机程序产品。

    Carbon implant for workfunction adjustment in replacement gate transistor
    185.
    发明授权
    Carbon implant for workfunction adjustment in replacement gate transistor 有权
    用于替换栅极晶体管功能调整的碳植入物

    公开(公告)号：US08536627B2

    公开(公告)日：2013-09-17

    申请号：US13623162

    申请日：2012-09-20

    Applicant: International Business Machines Corporation

    Inventor： Dechao Guo ,  Shu-Jen Han ,  Keith Kwong Hon Wong ,  Jun Yuan

    IPC: H01L29/80

    CPC classification number: H01L21/2822 ,  H01L21/26506 ,  H01L21/823412 ,  H01L21/823437 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545

    Abstract: A transistor includes a semiconductor body having a channel formed in the semiconductor body; a high dielectric constant gate insulator layer disposed over a surface of an upper portion of the channel; and a gate metal layer disposed over the high dielectric constant gate insulator layer. The channel contains Carbon implanted through the gate metal layer, the high dielectric constant gate insulator layer and the surface to form in the upper portion of the channel a Carbon-implanted region having a substantially uniform concentration of Carbon selected to establish a voltage threshold of the transistor.

    Abstract translation: 晶体管包括半导体本体，其具有形成在半导体本体中的沟道; 设置在所述通道的上部的表面上的高介电常数栅极绝缘体层; 以及设置在高介电常数栅绝缘体层上的栅极金属层。 通道包含通过栅极金属层注入的碳，高介电常数栅极绝缘体层和在沟道的上部部分中形成的表面，其具有基本均匀的碳浓度的碳注入区域，用于建立电压阈值 晶体管。

    Self-assembly of nanostructures
    187.
    发明授权
    Self-assembly of nanostructures 有权

    公开(公告)号：US11211560B2

    公开(公告)日：2021-12-28

    申请号：US16689371

    申请日：2019-11-20

    Applicant: International Business Machines Corporation

    Inventor： Shu-Jen Han

    IPC: H01L51/00 ,  C01B32/168 ,  B82Y40/00 ,  B82Y30/00

    Abstract: Sub-lithographic structures configured for selective placement of carbon nanotubes and methods of fabricating the same generally includes alternating conformal first and second layers provided on a topographical pattern formed in a dielectric layer. The conformal layers can be deposited by atomic layer deposition or chemical vapor deposition at thicknesses less than 5 nanometers. A planarized surface of the alternating conformal first and second layers provides an alternating pattern of exposed surfaces corresponding to the first and second layer, wherein a width of at least a portion of the exposed surfaces is substantially equal to the thickness of the corresponding first and second layers. The first layer is configured to provide an affinity for carbon nanotubes and the second layer does not have an affinity such that the carbon nanotubes can be selectively placed onto the exposed surfaces of the alternating pattern corresponding to the first layer.

    Multispectral plasmonic thermal imaging device
    190.
    发明授权
    Multispectral plasmonic thermal imaging device 有权

    公开(公告)号：US10830646B2

    公开(公告)日：2020-11-10

    申请号：US16380042

    申请日：2019-04-10

    Applicant: International Business Machines Corporation

    Inventor： Ali Afzali-Ardakani ,  Abram L. Falk ,  Damon B. Farmer ,  Shu-Jen Han ,  George S. Tulevski

    IPC: G01J5/00 ,  G01J5/04 ,  G01J5/60 ,  G01J5/08 ,  G01J5/02 ,  G01J5/20

    Abstract: A computer-implemented method of forming a thermal-based electronic image of an object that includes receiving electromagnetic radiation emitted by the object at an optically sensitive layer including a superpixel having a plurality of pixels. Each pixel of the plurality of pixels includes a plasmonic absorber having a characteristic resonance wavelength and that generates a radiance measurement of the electromagnetic radiation at its characteristic resonance wavelength. The method further provides for determining, at a processor, an emissivity and temperature for the electromagnetic radiation received at the superpixel using the radiance measurements obtained at the pixels of the superpixel. In addition, the method provides for forming an image of the object from the determined emissivity and temperature.

Patent Agency Ranking