公开(公告)号：US12002532B2

公开(公告)日：2024-06-04

申请号：US18121220

申请日：2023-03-14

Applicant: Rambus Inc.

Inventor： John Eric Linstadt ,  Frederick A. Ware

IPC: G11C29/42 ,  G11C8/18 ,  G11C29/18 ,  G11C29/44

CPC classification number: G11C29/42 ,  G11C8/18 ,  G11C29/18 ,  G11C29/44

Abstract: A memory component and a controller communicate commands and data with each other The commands to activate and then access data, and the data itself, are all communicated between a controller and the memory component at different times. The controller and memory component each calculate a respective error detecting code (EDC) values on the activate command information (e.g., bank address and row address) and store them indexed by the bank address. When the memory component is accessed, retrieved EDC values are combined with EDC values calculated from the access command information, and the data itself. The memory component transmits its combined EDC value to the controller for checking.

公开(公告)号：US11996160B2

公开(公告)日：2024-05-28

申请号：US17892291

申请日：2022-08-22

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Eric Linstadt ,  Carl W. Werner

IPC: G11C7/04 ,  G06F1/12 ,  G11C7/22 ,  G11C29/02 ,  G11C29/50 ,  H03K5/15 ,  H10N60/12

CPC classification number: G11C7/04 ,  G06F1/12 ,  G11C7/222 ,  G11C29/022 ,  G11C29/023 ,  G11C29/50012 ,  G11C2207/2254 ,  H03K5/15 ,  H10N60/12

Abstract: In a chip-to-chip signaling system includes at least one signaling link coupled between first and second ICs, the first IC has an interface coupled to the signaling link and timed by a first interface timing signal. The second IC has an interface coupled to the signaling link and timed by a second interface timing signal that is mesochronous with respect to the first interface timing signal. The second IC further has phase adjustment circuitry that adjusts a phase of the second interface timing signal using a digital counter implemented with Josephson-junction circuit elements.

公开(公告)号：US20240160587A1

公开(公告)日：2024-05-16

申请号：US18513246

申请日：2023-11-17

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Kenneth L. Wright ,  John Eric Linstadt ,  Craig Hampel

IPC: G06F13/16 ,  G06F3/06 ,  G06F11/10 ,  G06F12/0868 ,  G06F12/0888 ,  G06F12/0895 ,  G06F13/28 ,  G11C7/10 ,  G11C29/52

CPC classification number: G06F13/1678 ,  G06F3/0604 ,  G06F3/0613 ,  G06F3/0619 ,  G06F3/0634 ,  G06F3/0656 ,  G06F3/0673 ,  G06F11/1004 ,  G06F11/1068 ,  G06F12/0868 ,  G06F12/0888 ,  G06F12/0895 ,  G06F13/28 ,  G11C7/10 ,  G11C29/52 ,  G06F2212/1016 ,  G06F2212/1032 ,  G06F2212/403

Abstract: Memory controllers, devices, modules, systems and associated methods are disclosed. In one embodiment, a memory module includes a pin interface for coupling to a bus. The bus has a first width. The module includes at least one storage class memory (SCM) component and at least one DRAM component. The memory module operates in a first mode that utilizes all of the first width, and in a second mode that utilizes less than all of the first width.

公开(公告)号：US20240104036A1

公开(公告)日：2024-03-28

申请号：US18482268

申请日：2023-10-06

Applicant: Rambus Inc

Inventor： Frederick A. Ware ,  Ely Tsern ,  John Eric Linstadt ,  Thomas J. Giovannini ,  Kenneth L. Wright

IPC: G06F13/28 ,  G06F13/16 ,  G11C5/04 ,  G11C7/10

CPC classification number: G06F13/287 ,  G06F13/16 ,  G11C5/04 ,  G11C7/10 ,  G11C7/1045 ,  G06F2213/28

Abstract: The embodiments described herein describe technologies of dynamic random access memory (DRAM) components for high-performance, high-capacity registered memory modules, such as registered dual in-line memory modules (RDIMMs). One DRAM component may include a set of memory cells and steering logic. The steering logic may include a first data interface and a second data interface. The first and second data interfaces are selectively coupled to a controller component in a first mode and the first data interface is selectively coupled to the controller component in a second mode and the second data interface is selectively coupled to a second DRAM component in the second mode.

公开(公告)号：US20240095198A1

公开(公告)日：2024-03-21

申请号：US18480344

申请日：2023-10-03

Applicant: Rambus Inc.

Inventor： Thomas J. Giovannini ,  John Eric Linstadt ,  Catherine Chen

IPC: G06F13/16 ,  G06F13/40 ,  G06F13/42

CPC classification number: G06F13/1689 ,  G06F13/1673 ,  G06F13/1678 ,  G06F13/4022 ,  G06F13/4265

Abstract: A memory system supports single- and dual-memory-module configurations, both supporting point-to-point communication between a host (e.g., a memory controller) and the memory module or modules. Each memory module includes an address-buffer component, data-buffer components, and two sets of memory dies, each set termed a “timing rank,” that can be accessed independently. The one memory module is configured in a wide mode for the single-memory-module configuration, in which case both timing ranks work together, as a “package rank,” to communicate full-width data. Each of two memory modules are configured in a narrow mode for the dual-memory-module configuration, in which case one timing rank from each memory module communicates data in parallel to appear to the host as single package ranks. The data-buffer components support separate and configurable write and read delays for the different timing ranks on each module to provide read and write leveling within and between memory modules.

公开(公告)号：US20240095134A1

公开(公告)日：2024-03-21

申请号：US18373219

申请日：2023-09-26

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Brent S. Haukness ,  John Eric Linstadt ,  Scott C. Best

IPC: G06F11/20 ,  G11C11/4093 ,  G11C29/52

CPC classification number: G06F11/2094 ,  G11C11/4093 ,  G11C29/52 ,  G06F2201/82

Abstract: A memory module is disclosed. The memory module includes a substrate, and respective first, second and third memory devices. The first memory device is of a first type disposed on the substrate and has addressable storage locations. The second memory device is also of the first type, and includes storage cells dedicated to store failure address information associated with defective storage locations in the first memory device. The third memory device is of the first type and includes storage cells dedicated to substitute as storage locations for the defective storage locations.

公开(公告)号：US11900984B2

公开(公告)日：2024-02-13

申请号：US18104069

申请日：2023-01-31

Applicant: Rambus Inc.

Inventor： Torsten Partsch ,  John Eric Linstadt ,  Helena Handschuh

IPC: G11C7/00 ,  G11C11/406 ,  G11C11/4091 ,  G11C11/4076 ,  G11C11/4094 ,  G11C11/408

CPC classification number: G11C11/40626 ,  G11C11/4076 ,  G11C11/4085 ,  G11C11/4091 ,  G11C11/4094

Abstract: A block of dynamic memory in a DRAM device is organized to share a common set of bitlines may be erased/destroyed/randomized by concurrently activating multiple (or all) of the wordlines of the block. The data held in the sense amplifiers and cells of an active wordline may be erased by precharging the sense amplifiers and then writing precharge voltages into the cells of the open row. Rows are selectively configured to either be refreshed or not refreshed. The rows that are not refreshed will, after a time, lose their contents thereby reducing the time interval for attack. An external signal can cause the isolation of a memory device or module and initiation of automatic erasure of the memory contents of the device or module using one of the methods disclosed herein. The trigger for the external signal may be one or more of temperature changes/conditions, loss of power, and/or external commands from a controller.

公开(公告)号：US20240020249A1

公开(公告)日：2024-01-18

申请号：US18365696

申请日：2023-08-04

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Ely Tsern ,  John Eric Linstadt ,  Thomas J. Giovannini ,  Craig E. Hampel ,  Scott C. Best ,  John Yan

IPC: G06F13/16

CPC classification number: G06F13/1678 ,  G06F13/1673 ,  G06F13/1694

Abstract: Described are motherboards with memory-module sockets that accept legacy memory modules for backward compatibility or accept a greater number of configurable modules in support of increased memory capacity. The configurable modules can be backward compatible with legacy motherboards. Equipped with the configurable modules, the motherboards support memory systems with high signaling rates and capacities.

公开(公告)号：US11790973B2

公开(公告)日：2023-10-17

申请号：US17376032

申请日：2021-07-14

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Eric Linstadt ,  Brent Steven Haukness ,  Kenneth L. Wright ,  Thomas Vogelsang

IPC: G11C11/34 ,  G11C11/403 ,  G11C11/4097 ,  G11C11/4096 ,  G11C8/08 ,  G11C7/10 ,  G11C7/18 ,  G11C5/02 ,  G11C11/408 ,  G06F12/06 ,  G11C11/406 ,  G11C11/409 ,  G11C11/4091

CPC classification number: G11C11/403 ,  G06F12/06 ,  G11C5/025 ,  G11C7/1018 ,  G11C7/1045 ,  G11C7/1096 ,  G11C7/18 ,  G11C8/08 ,  G11C11/408 ,  G11C11/409 ,  G11C11/4085 ,  G11C11/4096 ,  G11C11/4097 ,  G11C11/40618 ,  G11C11/4091

Abstract: A memory component includes a first memory bank. The first memory bank has a plurality of sub-arrays having sub-rows of memory elements. The memory component includes a write driver, coupled to the first memory bank, to perform a write operation of an entire sub-row of a sub-array. To perform the write operation, the write driver is to load a burst of write data to the memory bank. The memory bank may then activate a plurality of sense amplifiers associated with a plurality of memory elements of the entire sub-row to load the burst of write data to the plurality of sense amplifiers.

公开(公告)号：US20230325540A1

公开(公告)日：2023-10-12

申请号：US18130362

申请日：2023-04-03

Applicant: Rambus Inc.

Inventor： Evan Lawrence Erickson ,  John Eric Linstadt

IPC: G06F21/79 ,  G06F21/85 ,  G06F21/60

CPC classification number: G06F21/79 ,  G06F21/85 ,  G06F21/602

Abstract: A buffer integrated circuit (IC) chip is disclosed. The buffer IC chip includes host interface circuitry to receive a request from at least one host. The request includes at least one command to access a memory. Memory interface circuitry couples to the memory. Message authentication circuitry performs a verification operation on the received request. Selective containment circuitry, during a containment mode of operation, (1) inhibits changes to the memory in response to the at least one command until completion of the verification operation, and (2) during performance of the verification operation, carries out at least one non-memory modifying sub-operation associated with the at least one command.