公开(公告)号：US09136293B2

公开(公告)日：2015-09-15

申请号：US13606289

申请日：2012-09-07

Applicant: Kuo-Chung Yee ,  Chun Hui Yu

Inventor： Kuo-Chung Yee ,  Chun Hui Yu

IPC: H01L27/146 ,  H01L23/48

CPC classification number: H01L27/14632 ,  H01L23/481 ,  H01L27/14618 ,  H01L27/14621 ,  H01L27/14636 ,  H01L27/1464 ,  H01L27/14641 ,  H01L27/14683 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods and apparatus for integrating a CMOS image sensor and an image signal processor (ISP) together using an interposer to form a system in package device module are disclosed. The device module may comprise an interposer with a substrate. An interposer contact is formed within the substrate. A sensor device may be bonded to a surface of the interposer, wherein a sensor contact is bonded to a first end of the interposer contact. An ISP may be connected to the interposer, by bonding an ISP contact in the ISP to a second end of the interposer contact. An underfill layer may fill a gap between the interposer and the ISP. A printed circuit board (PCB) may further be connected to the interposer by way of a solder ball connected to another interposer contact. A thermal interface material may be in contact with the ISP and the PCB.

Abstract translation: 公开了使用插入器将CMOS图像传感器和图像信号处理器（ISP）集成在一起以形成封装器件模块中的系统的方法和装置。 器件模块可以包括具有衬底的插入器。 在衬底内形成插入物接触。 传感器装置可以结合到插入件的表面，其中传感器触点被结合到插入件触点的第一端。 ISP可以通过将ISP中的ISP联系人连接到插入器联系人的第二端来连接到插入器。 底层填充层可以填补插入件和ISP之间的间隙。 印刷电路板（PCB）还可以通过连接到另一插入器触点的焊球连接到插入器。 热界面材料可能与ISP和PCB接触。

公开(公告)号：US08741691B2

公开(公告)日：2014-06-03

申请号：US13452636

申请日：2012-04-20

Applicant: Kuo-Chung Yee ,  Chun Hui Yu

Inventor： Kuo-Chung Yee ,  Chun Hui Yu

IPC: H01L21/00

CPC classification number: H01L23/49811 ,  H01L21/561 ,  H01L21/563 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/498 ,  H01L23/49827 ,  H01L23/49894 ,  H01L24/10 ,  H01L24/81 ,  H01L24/97 ,  H01L2224/10 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/81 ,  H01L2224/81005 ,  H01L2224/97 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/00

Abstract: A method of fabricating a three dimensional integrated circuit comprises forming a redistribution layer on a first side of a packaging component, forming a holding chamber in the redistribution layer, attaching an integrated circuit die on the first side of the packaging component, wherein an interconnect bump of the integrated circuit die is inserted into the holding chamber, applying a reflow process to the integrated circuit die and the packaging component and forming an encapsulation layer on the packaging component.

Abstract translation: 一种制造三维集成电路的方法包括在包装部件的第一侧上形成再分配层，在再分布层中形成保持室，将集成电路管芯附接在包装部件的第一侧上，其中互连凸块 的集成电路管芯插入到保持室中，对集成电路管芯和封装部件进行回流处理，并在封装部件上形成封装层。

公开(公告)号：US20130037950A1

公开(公告)日：2013-02-14

申请号：US13206694

申请日：2011-08-10

Applicant: Chun Hui Yu ,  Chih-Hang Tung ,  Tung-Liang Shao ,  Chen-Hua Yu ,  Da-Yuan Shih

Inventor： Chun Hui Yu ,  Chih-Hang Tung ,  Tung-Liang Shao ,  Chen-Hua Yu ,  Da-Yuan Shih

IPC: H01L23/485 ,  H01L21/82 ,  H01L21/56

CPC classification number: H01L23/481 ,  H01L21/563 ,  H01L21/568 ,  H01L21/76805 ,  H01L21/76838 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5226 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/19 ,  H01L24/24 ,  H01L24/82 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/19 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2224/73267 ,  H01L2224/81005 ,  H01L2224/8203 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06548 ,  H01L2225/06568 ,  H01L2924/01029 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18162 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2224/03 ,  H01L2224/83005

Abstract: A multi-chip wafer level package comprises three stacked semiconductor dies. A first semiconductor die is embedded in a first photo-sensitive material layer. A second semiconductor die is stacked on top of the first semiconductor die wherein the second semiconductor die is face-to-face coupled to the first semiconductor die. A third semiconductor die is back-to-back attached to the second semiconductor die. Both the second semiconductor die and the third semiconductor die are embedded in a second photo-sensitive material layer. The multi-chip wafer level package further comprises a plurality of through assembly vias formed in the first photo-sensitive material layer and the second photo-sensitive material layer.

Abstract translation: 多芯片晶片级封装包括三个堆叠的半导体管芯。 第一半导体管芯被嵌入在第一光敏材料层中。 第二半导体管芯堆叠在第一半导体管芯的顶部上，其中第二半导体管芯与第一半导体管芯面对面连接。 第三半导体管芯背靠背连接到第二半导体管芯。 第二半导体管芯和第三半导体管芯都嵌入第二光敏材料层。 多芯片晶片级封装还包括形成在第一光敏材料层和第二光敏材料层中的多个通过组装通孔。

公开(公告)号：US20120098123A1

公开(公告)日：2012-04-26

申请号：US12953130

申请日：2010-11-23

Applicant: Chen-Hua Yu ,  Chun Hui Yu ,  Jing-Cheng Lin

Inventor： Chen-Hua Yu ,  Chun Hui Yu ,  Jing-Cheng Lin

IPC: H01L23/498

CPC classification number: H01L25/0655 ,  H01L21/563 ,  H01L21/568 ,  H01L23/3157 ,  H01L23/36 ,  H01L23/42 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/81 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/97 ,  H01L2924/00011 ,  H01L2924/01029 ,  H01L2924/01322 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/81805

Abstract: Apparatus and methods for providing a molded chip interposer structure and assembly. A molded chip structure having at least two integrated circuit dies disposed within a mold compound is provided having the die bond pads on the bottom surface; and solder bumps are formed in the openings of a dielectric layer on the bottom surface, the solder bumps forming connections to the bond pads. An interposer having a die side surface and a board side surface is provided having bump lands receiving the solder bumps of the molded chip structure on the die side of the interposer. An underfill layer is formed between the die side of the interposer and the bottom surface of the molded chip structure surrounding the solder bumps. Methods for forming the molded chip interposer structure are disclosed.

Abstract translation: 用于提供模制芯片插入件结构和组装的装置和方法。 提供具有设置在模具化合物内的至少两个集成电路管芯的模制芯片结构，其具有底表面上的管芯接合焊盘; 并且在底表面上的电介质层的开口中形成焊料凸块，焊料凸块形成与焊盘的连接。 具有裸片侧表面和电路板侧表面的插入件设置有凸起焊盘，其在插入件的裸片侧接收模制芯片结构的焊料凸块。 在插入件的裸片侧和围绕焊料凸块的模制芯片结构的底表面之间形成底部填充层。 公开了用于形成模制芯片内插器结构的方法。

公开(公告)号：US20120063090A1

公开(公告)日：2012-03-15

申请号：US12878319

申请日：2010-09-09

Applicant: Yi-Li HSIAO ,  Chen-Hua YU ,  Da-Yuan SHIH ,  Chih-Hang TUNG ,  Chun Hui YU

Inventor： Yi-Li HSIAO ,  Chen-Hua YU ,  Da-Yuan SHIH ,  Chih-Hang TUNG ,  Chun Hui YU

IPC: H01L23/34 ,  H01L21/50

CPC classification number: H01L23/44 ,  H01L23/473 ,  H01L24/14 ,  H01L24/16 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/165 ,  H01L25/18 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/06589 ,  H01L2924/01019 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/1461 ,  H01L2924/157 ,  H01L2924/00

Abstract: An apparatus for cooling a stacked die package comprises a substrate, a first die above the substrate, a second die above the first die, and a housing containing the first and second dies. The housing seals the first and second dies from the environment. The apparatus further includes a cooling fluid in fluid communication with the first die and the second die to transfer the heat from the dies to the housing.

Abstract translation: 一种用于冷却堆叠管芯封装的装置，包括：衬底，在衬底上方的第一裸片，在第一裸片上方的第二裸片;以及容纳第一和第二裸片的外壳。 壳体将第一和第二模具与环境密封。 该装置还包括与第一模具和第二模具流体连通的冷却流体，以将来自模具的热量传递到壳体。

公开(公告)号：US07884461B2

公开(公告)日：2011-02-08

申请号：US12217086

申请日：2008-06-30

Applicant: Dyi-Chung Hu ,  Chun-Hui Yu

Inventor： Dyi-Chung Hu ,  Chun-Hui Yu

IPC: H01L23/48

CPC classification number: H01L23/5389 ,  H01L21/568 ,  H01L24/19 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/06181 ,  H01L2224/24227 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/18162 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2924/00

Abstract: The present invention discloses a structure of package comprising: a substrate with a die receiving through hole and a contact conductive via formed therein, a die disposed within the die receiving through hole, a surrounding material filled in the gap except the die area of the die receiving though hole, a re-distribution layer formed on the substrate and coupled to the contact conductive via, a protection layer formed over the re-distribution layer, a cover material formed over the protection layer; and a terminal contact pad formed on the lower surface of the substrate and under the contact conductive via and the die to couple the contact conductive via.

Abstract translation: 本发明公开了一种包装体的结构，其特征在于，包括具有模片接收通孔的基板和形成在其中的接触导电通孔，设置在模具接收通孔内的模具，填充在除模具的模具区域之外的间隙中的周围材料 接收通孔，形成在基板上并耦合到接触导电通孔的再分布层，形成在再分布层上的保护层，形成在保护层上的覆盖材料; 以及端子接触焊盘，其形成在所述基板的下表面上并且在所述接触导电通孔和所述管芯下方以耦合所述接触导电通孔。

公开(公告)号：US20090321915A1

公开(公告)日：2009-12-31

申请号：US12217086

申请日：2008-06-30

Applicant: Dyi-Chung Hu ,  Chun-Hui Yu

Inventor： Dyi-Chung Hu ,  Chun-Hui Yu

IPC: H01L23/48 ,  H01L21/52

CPC classification number: H01L23/5389 ,  H01L21/568 ,  H01L24/19 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/06181 ,  H01L2224/24227 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/18162 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2924/00

Abstract: The present invention discloses a structure of package comprising: a substrate with a die receiving through hole and a contact conductive via formed therein, a die disposed within the die receiving through hole, a surrounding material filled in the gap except the die area of the die receiving though hole, a re-distribution layer formed on the substrate and coupled to the contact conductive via, a protection layer formed over the re-distribution layer, a cover material formed over the protection layer; and a terminal contact pad formed on the lower surface of the substrate and under the contact conductive via and the die to couple the contact conductive via.

Abstract translation: 本发明公开了一种包装体的结构，其特征在于，包括具有模片接收通孔的基板和形成在其中的接触导电通孔，设置在模具接收通孔内的模具，填充在除模具的模具区域之外的间隙中的周围材料 接收通孔，形成在基板上并耦合到接触导电通孔的再分布层，形成在再分布层上的保护层，形成在保护层上的覆盖材料; 以及端子接触焊盘，其形成在所述基板的下表面上并且在所述接触导电通孔和所述管芯下方以耦合所述接触导电通孔。

公开(公告)号：US07476565B2

公开(公告)日：2009-01-13

申请号：US11799923

申请日：2007-05-03

Applicant: Wen-Kun Yang ,  Wen-Bin Sun ,  Hsi-Ying Yuan ,  Chun Hui Yu

Inventor： Wen-Kun Yang ,  Wen-Bin Sun ,  Hsi-Ying Yuan ,  Chun Hui Yu

IPC: H01L21/44 ,  H01L21/48 ,  H01L21/50

CPC classification number: H01L21/6835 ,  H01L23/5389 ,  H01L24/29 ,  H01L24/83 ,  H01L2224/2919 ,  H01L2224/8385 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/01094 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00

Abstract: A filling paste structure and process of wafer level package is disclosed. The process comprises filling an adhesive material to fill among plurality of dice and cover the plurality of dice. The pluralities of dice are adhered to glue pattern with viscosity in common state formed on a removable substrate. A rigid substrate is coated by adhesive material to adhere the dice. Then, pluralities of dice are departed from the glue pattern by a special environment after attaching the rigid base substrate.

Abstract translation: 公开了一种填充浆料结构和晶片级封装的工艺。 该方法包括填充粘合剂材料以填充多个骰子并覆盖多个骰子。 多个骰子粘附在形成在可移除基底上的共同状态下的粘度的胶图案上。 用粘合剂材料涂覆刚性基材以粘附骰子。 然后，在连接刚性基底之后，多个骰子由特殊的环境离开胶合图案。

公开(公告)号：US07453148B2

公开(公告)日：2008-11-18

申请号：US11613247

申请日：2006-12-20

Applicant: Wen-Kun Yang ,  Chun-Hui Yu ,  Chao-Nan Chou ,  Chih-Wei Lin ,  Ching-Shun Huang

Inventor： Wen-Kun Yang ,  Chun-Hui Yu ,  Chao-Nan Chou ,  Chih-Wei Lin ,  Ching-Shun Huang

IPC: H01L23/48

CPC classification number: H01L23/5389 ,  H01L24/19 ,  H01L2224/04105 ,  H01L2224/20 ,  H01L2224/73267 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/351 ,  H01L2924/00

Abstract: The present invention provides a structure of elastic dielectric layers with certain through holes adjacent to the angle of a RDL of WLP to absorb the stress. The elastic dielectric layer is made from silicone based materials with specific range of CTE, elongation rate and hardness, which can improve the mechanical reliability of the structure during temperature cycling test. The CTE difference between the RDL and the elastic dielectric material still may cause the elastic dielectric layer crack; to solve this problem, The present invention further provides a structure of dielectric layers with certain open through holes adjacent to the curve portion of a RDL of WLP which can reduce the stress accumulated at area of the dielectric layer adjacent to the RDL/dielectric layer interface to solve the crack problem of the dielectric layer.

Abstract translation: 本发明提供了具有与WLP的RDL的角度相邻的某些通孔以吸收应力的弹性介电层的结构。 弹性介电层由具有特定范围的CTE，伸长率和硬度的硅酮基材料制成，这可以在温度循环测试期间提高结构的机械可靠性。 RDL和弹性介电材料之间的CTE差异仍然可能导致弹性介电层裂纹; 为了解决这个问题，本发明还提供了具有与WLP的RDL的曲线部分相邻的某些开放通孔的电介质层的结构，其可以减少在与RDL /介电层界面相邻的介电层的面积处积累的应力 以解决电介质层的裂纹问题。

公开(公告)号：US20080174008A1

公开(公告)日：2008-07-24

申请号：US11624629

申请日：2007-01-18

Applicant: Wen-Kun Yang ,  Chun-Hui Yu ,  Chihwei Lin ,  Chao-nan Chou

Inventor： Wen-Kun Yang ,  Chun-Hui Yu ,  Chihwei Lin ,  Chao-nan Chou

IPC: H01L25/065 ,  H01L21/50

CPC classification number: G11C5/02 ,  G11C5/025 ,  G11C5/063 ,  H01L23/49855 ,  H01L23/5389 ,  H01L24/24 ,  H01L25/0657 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05026 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05548 ,  H01L2224/05569 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/16 ,  H01L2224/24227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/73267 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2924/01029 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/15153 ,  H01L2924/18161 ,  H01L2924/19105 ,  H01L2924/00014 ,  H01L2924/01028 ,  H01L2924/013

Abstract: The present invention provides a structure of memory card comprising a substrate with a die receiving cavity formed within an upper surface of the substrate and a through hole structure formed there through, traces formed within the substrate; a first die disposed within the die receiving cavity; a first dielectric layer formed on the first die and the substrate; a first re-distribution layer (RDL) formed on the first dielectric layer, wherein the first RDL is coupled to the first die and the traces; a second dielectric layer formed over the first RDL; a second die disposed on the second dielectric layer; a third dielectric layer formed over the second dielectric layer and the second die; a second RDL formed on the third dielectric layer, wherein the second RDL is coupled to the second die and the first RDL; a forth dielectric layer formed over the second RDL; a third die formed over the forth dielectric layer and coupled to the second RDL; a fifth dielectric layer formed around the third die; and a plastic cover enclosed the first, second and third dice.

Abstract translation: 本发明提供了一种存储卡的结构，该结构包括一个基板，该基板在该基板的上表面内形成有一个模具接收腔，以及一个通孔结构，其形成在该基板内; 设置在所述模具容纳腔内的第一模具; 形成在所述第一管芯和所述基板上的第一电介质层; 形成在所述第一介电层上的第一再分布层（RDL），其中所述第一RDL耦合到所述第一裸片和所述迹线; 形成在所述第一RDL上的第二电介质层; 设置在所述第二电介质层上的第二管芯; 形成在所述第二介电层和所述第二管芯上的第三电介质层; 形成在所述第三介电层上的第二RDL，其中所述第二RDL耦合到所述第二裸片和所述第一RDL; 形成在所述第二RDL上的第四电介质层; 形成在所述第四电介质层上并耦合到所述第二RDL的第三裸片; 形成在第三模具周围的第五电介质层; 和一个塑料盖包围第一，第二和第三个骰子。