公开(公告)号：US20120175789A1

公开(公告)日：2012-07-12

申请号：US12987202

申请日：2011-01-10

申请人： Mukta G. Farooq ,  Troy L. Graves-Abe ,  Robert Hannon ,  Emily R. Kinser ,  William F. Landers ,  Kevin S. Patrarca ,  Richard P. Volant ,  Kevin R. Winstel

发明人： Mukta G. Farooq ,  Troy L. Graves-Abe ,  Robert Hannon ,  Emily R. Kinser ,  William F. Landers ,  Kevin S. Patrarca ,  Richard P. Volant ,  Kevin R. Winstel

IPC分类号： H01L23/544 ,  H01L21/02

CPC分类号： H01L21/76898 ,  H01L21/8221 ,  H01L23/544 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L25/0657 ,  H01L2223/54426 ,  H01L2224/29187 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/8385 ,  H01L2224/83896 ,  H01L2224/9202 ,  H01L2224/94 ,  H01L2225/06541 ,  H01L2225/06593 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2224/83

摘要： Disclosed are a structure including alignment marks and a method of forming alignment marks in three dimensional (3D) structures. The method includes forming apertures in a first surface of a first semiconductor substrate; joining the first surface of the first semiconductor substrate to a first surface of a second semiconductor substrate; thinning the first semiconductor on a second surface of the first semiconductor substrate to provide optical contrast between the apertures and the first semiconductor substrate; and aligning a feature on the second surface of the first semiconductor substrate using the apertures as at least one alignment mark.

摘要翻译： 公开了包括对准标记的结构和在三维（3D）结构中形成对准标记的方法）。 该方法包括在第一半导体衬底的第一表面中形成孔; 将第一半导体衬底的第一表面接合到第二半导体衬底的第一表面; 在第一半导体衬底的第二表面上使第一半导体薄化以提供孔和第一半导体衬底之间的光学对比度; 以及使用所述孔将所述第一半导体衬底的所述第二表面上的特征对准为至少一个对准标记。

公开(公告)号：US08546961B2

公开(公告)日：2013-10-01

申请号：US12987202

申请日：2011-01-10

申请人： Mukta G. Farooq ,  Troy L. Graves-Abe ,  Robert Hannon ,  Emily R. Kinser ,  William F. Landers ,  Kevin S. Petrarca ,  Richard P. Volant ,  Kevin R. Winstel

发明人： Mukta G. Farooq ,  Troy L. Graves-Abe ,  Robert Hannon ,  Emily R. Kinser ,  William F. Landers ,  Kevin S. Petrarca ,  Richard P. Volant ,  Kevin R. Winstel

IPC分类号： H01L23/544 ,  H01L21/02

CPC分类号： H01L21/76898 ,  H01L21/8221 ,  H01L23/544 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L25/0657 ,  H01L2223/54426 ,  H01L2224/29187 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/8385 ,  H01L2224/83896 ,  H01L2224/9202 ,  H01L2224/94 ,  H01L2225/06541 ,  H01L2225/06593 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2224/83

摘要： Disclosed are a structure including alignment marks and a method of forming alignment marks in three dimensional (3D) structures. The method includes forming apertures in a first surface of a first semiconductor substrate; joining the first surface of the first semiconductor substrate to a first surface of a second semiconductor substrate; thinning the first semiconductor on a second surface of the first semiconductor substrate to provide optical contrast between the apertures and the first semiconductor substrate; and aligning a feature on the second surface of the first semiconductor substrate using the apertures as at least one alignment mark.

摘要翻译： 公开了包括对准标记的结构和在三维（3D）结构中形成对准标记的方法）。 该方法包括在第一半导体衬底的第一表面中形成孔; 将第一半导体衬底的第一表面接合到第二半导体衬底的第一表面; 在第一半导体衬底的第二表面上使第一半导体薄化以提供孔和第一半导体衬底之间的光学对比度; 以及使用所述孔将所述第一半导体衬底的所述第二表面上的特征对准为至少一个对准标记。

公开(公告)号：US08487425B2

公开(公告)日：2013-07-16

申请号：US13167107

申请日：2011-06-23

申请人： Paul S Andry ,  Mukta G Farooq ,  Robert Hannon ,  Subramanian S Iyer ,  Emily R Kinser ,  Cornelia K Tsang ,  Richard P Volant

发明人： Paul S Andry ,  Mukta G Farooq ,  Robert Hannon ,  Subramanian S Iyer ,  Emily R Kinser ,  Cornelia K Tsang ,  Richard P Volant

IPC分类号： H01L23/04 ,  H01L23/48

CPC分类号： H01L21/76846 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present disclosure provides a thermo-mechanically reliable copper TSV and a technique to form such TSV during BEOL processing. The TSV constitutes an annular trench which extends through the semiconductor substrate. The substrate defines the inner and outer sidewalls of the trench, which sidewalls are separated by a distance within the range of 5 to 10 microns. A conductive path comprising copper or a copper alloy extends within said trench from an upper surface of said first dielectric layer through said substrate. The substrate thickness can be 60 microns or less. A dielectric layer having interconnect metallization conductively connected to the conductive path is formed directly over said annular trench.

摘要翻译： 本公开提供了热机械可靠的铜TSV和在BEOL处理期间形成这种TSV的技术。 TSV构成延伸穿过半导体衬底的环形沟槽。 衬底限定沟槽的内侧壁和外侧壁，该侧壁分隔5至10微米的距离。 包括铜或铜合金的导电路径从所述第一介电层的上表面通过所述衬底在所述沟槽内延伸。 基板厚度可以为60微米或更小。 具有导电连接到导电路径的互连金属化的电介质层直接形成在所述环形沟槽上。

公开(公告)号：US20120168952A1

公开(公告)日：2012-07-05

申请号：US13418261

申请日：2012-03-12

申请人： Mukta G. Farooq ,  Emily R. Kinser ,  Ian D. Melville ,  Krystyna W. Semkow

发明人： Mukta G. Farooq ,  Emily R. Kinser ,  Ian D. Melville ,  Krystyna W. Semkow

IPC分类号： H01L23/522 ,  H01L21/768

CPC分类号： H01L21/02697 ,  H01L23/53238 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0401 ,  H01L2224/05006 ,  H01L2224/05007 ,  H01L2224/05016 ,  H01L2224/05026 ,  H01L2224/05027 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05157 ,  H01L2224/05187 ,  H01L2224/05562 ,  H01L2224/05572 ,  H01L2224/131 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/15787 ,  H01L2924/04953 ,  H01L2924/01014 ,  H01L2224/05552 ,  H01L2924/00

摘要： Disclosed is a process of making a semiconductor device wherein an insulation layer has a copper plug in contact with the last wiring layer of the device. There may also be a barrier layer separating the copper plug from the insulation layer. There may also be a cap layer over the copper plug to protect it from oxidation. There may also be a dielectric layer over the cap layer.

摘要翻译： 公开了制造半导体器件的方法，其中绝缘层具有与器件的最后布线层接触的铜插塞。 还可以存在将铜塞与绝缘层分离的阻挡层。 在铜塞上方也可能有一个盖层，以防止它被氧化。 在盖层上还可以存在介电层。

公开(公告)号：US08039964B2

公开(公告)日：2011-10-18

申请号：US12038241

申请日：2008-02-27

申请人： Mukta G. Farooq ,  Emily R. Kinser

发明人： Mukta G. Farooq ,  Emily R. Kinser

IPC分类号： H01L23/48 ,  H01L23/52

CPC分类号： H01L21/76831 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76829 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05572 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05666 ,  H01L2224/11 ,  H01L2224/13006 ,  H01L2924/0002 ,  H01L2924/00 ,  H01L2924/00014

摘要： A line trough and a via cavity are formed within a dielectric layer comprising a fluorosilicate glass (FSG) layer. A fluorine depleted adhesion layer is formed within the line trough and the via cavity either by a plasma treatment that removes fluorine from exposed surfaces of the FSG layer, or by deposition of a substantially fluorine-free dielectric layer. Metal is deposited within the line trough and the via cavity to form a metal line and a metal via. The fluorine depleted adhesion layer provides enhanced adhesion to the metal line compared with prior art structures in which a metal line directly contacts a FSG layer. The enhanced adhesion of metal with an underlying dielectric layer provides higher resistance to delamination for a semiconductor package employing lead-free C4 balls on a metal interconnect structure.

摘要翻译： 在包含氟硅酸盐玻璃（FSG）层的电介质层内形成线槽和通孔。 通过从FSG层的暴露表面除去氟的等离子体处理或通过沉积基本上无氟的介电层，在管线槽和通孔内形成氟贫化粘合层。 金属沉积在管线槽和通孔腔内以形成金属线和金属通孔。 与其中金属线直接接触FSG层的现有技术结构相比，氟贫化粘合层提供对金属线的增强的粘合性。 金属与底层电介质层的增强的粘附性对于在金属互连结构上使用无铅C4球的半导体封装提供更高的剥离性。

公开(公告)号：US08022543B2

公开(公告)日：2011-09-20

申请号：US12054713

申请日：2008-03-25

申请人： Mukta G. Farooq ,  Robert Hannon ,  Emily R. Kinser ,  Ian D. Melville

发明人： Mukta G. Farooq ,  Robert Hannon ,  Emily R. Kinser ,  Ian D. Melville

IPC分类号： H01L23/48

CPC分类号： H01L24/11 ,  H01L2224/0401 ,  H01L2224/05018 ,  H01L2224/05022 ,  H01L2224/05026 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05558 ,  H01L2224/05572 ,  H01L2224/0558 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2224/05552 ,  H01L2924/00014 ,  H01L2924/013

摘要： A first metallic diffusion barrier layer is formed on a last level metal plate exposed in an opening of a passivation layer. Optionally, a metallic adhesion promotion layer is formed on the first metallic diffusion barrier layer. An elemental metal conductive layer is formed on the metallic adhesion promotion layer, which provides a highly conductive structure that distributes current uniformly due to the higher electrical conductivity of the material than the layers above or below. A stack of the second metallic diffusion barrier layer and a wetting promotion layer is formed, on which a C4 ball is bonded. The elemental metal conductive layer distributes the current uniformly within the underbump metallurgy structure, which induces a more uniform current distribution in the C4 ball and enhanced electromigration resistance of the C4 ball.

摘要翻译： 第一金属扩散阻挡层形成在暴露在钝化层的开口中的最后一级金属板上。 任选地，在第一金属扩散阻挡层上形成金属粘附促进层。 在金属粘合促进层上形成元素金属导电层，其提供高导电性结构，其由于材料的导电性高于或高于上述层而导致电流均匀分布。 形成第二金属扩散阻挡层和润湿促进层的叠层，其上结合有C4球。 元素金属导电层将电流均匀分布在下焊管冶金结构内，从而在C4球中引起更均匀的电流分布，提高C4球的电迁移阻力。

公开(公告)号：US20110171827A1

公开(公告)日：2011-07-14

申请号：US12687282

申请日：2010-01-14

申请人： Mukta G. Farooq ,  Emily R. Kinser ,  Richard Wise ,  Hakeem Yusuff

发明人： Mukta G. Farooq ,  Emily R. Kinser ,  Richard Wise ,  Hakeem Yusuff

IPC分类号： H01L21/768

CPC分类号： H01L21/76847 ,  H01L21/0337 ,  H01L21/32136 ,  H01L21/76898 ,  H01L23/481 ,  H01L25/0657 ,  H01L25/50 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： A method includes patterning a photoresist layer on a structure to define an opening and expose a first planar area on a substrate layer, etching the exposed planar area to form a cavity having a first depth in the structure, removing a second portion of the photoresist to expose a second planar area on the substrate layer, forming a doped portion in the second planar area, and etching the cavity to expose a first conductor in the structure and the doped portion to expose a second conductor in the structure.

摘要翻译： 一种方法包括在结构上图案化光致抗蚀剂层以限定开口并暴露衬底层上的第一平面区域，蚀刻暴露的平面区域以形成在结构中具有第一深度的空腔，将光致抗蚀剂的第二部分去除 在衬底层上露出第二平面区域，在第二平面区域中形成掺杂部分，并且蚀刻腔体以暴露结构中的第一导体和掺杂部分以暴露结构中的第二导体。

公开(公告)号：US09406561B2

公开(公告)日：2016-08-02

申请号：US12426466

申请日：2009-04-20

申请人： Mukta G. Farooq ,  Robert Hannon ,  Subramanian S. Iyer ,  Emily R. Kinser

发明人： Mukta G. Farooq ,  Robert Hannon ,  Subramanian S. Iyer ,  Emily R. Kinser

IPC分类号： H01L21/768 ,  H01L25/065 ,  H01L25/00 ,  H01L23/00

CPC分类号： H01L21/76898 ,  H01L24/06 ,  H01L24/80 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/06181 ,  H01L2224/08146 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/80896 ,  H01L2224/8385 ,  H01L2224/9202 ,  H01L2224/94 ,  H01L2225/06541 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2224/83 ,  H01L2224/80 ,  H01L2924/00

摘要： A method of implementing three-dimensional (3D) integration of multiple integrated circuit (IC) devices includes forming a first insulating layer over a first IC device; forming a second insulating layer over a second IC device; forming a 3D, bonded IC device by aligning and bonding the first insulating layer to the second insulating layer so as to define a bonding interface therebetween, defining a first set of vias within the 3D bonded IC device, the first set of vias landing on conductive pads located within the first IC device, and defining a second set of vias within the 3D bonded IC device, the second set of vias landing on conductive pads located within the second device, such that the second set of vias passes through the bonding interface; and filling the first and second sets of vias with a conductive material.

摘要翻译： 实现多集成电路（IC）器件的三维（3D）集成的方法包括在第一IC器件上形成第一绝缘层; 在第二IC器件上形成第二绝缘层; 通过将第一绝缘层对准和结合到第二绝缘层来形成3D粘合IC器件，以便在它们之间限定其间的接合界面，限定3D结合IC器件内的第一组通孔，第一组通孔在导电 位于所述第一IC器件内的焊盘，以及限定所述3D结合IC器件内的第二组通孔，所述第二组通孔着陆在位于所述第二器件内的导电焊盘上，使得所述第二组通孔穿过所述接合界面; 以及用导电材料填充第一组和第二组通孔。

公开(公告)号：US09059175B2

公开(公告)日：2015-06-16

申请号：US13297338

申请日：2011-11-16

申请人： Mukta G. Farooq ,  Emily R. Kinser

发明人： Mukta G. Farooq ,  Emily R. Kinser

IPC分类号： H01L23/62 ,  H01L23/525 ,  H01L27/10

CPC分类号： H01L23/5258 ,  H01L23/5256 ,  H01L27/101 ,  H01L2924/0002 ,  H01L2924/00

摘要： In one embodiment, the invention provides a back-end-of-line (BEOL) line fuse structure. The BEOL line fuse structure includes: a line including a plurality of grains of conductive crystalline material; wherein the plurality of grains in a region between the first end and a second end include an average grain size that is smaller than a nominal grain size of the plurality of grains in a remaining portion of the line.

摘要翻译： 在一个实施例中，本发明提供一种后端行（BEOL）线路熔丝结构。 BEOL线熔丝结构包括：包括多个导电结晶材料颗粒的线; 其中在所述第一端和第二端之间的区域中的所述多个晶粒包括平均晶粒尺寸，所述平均晶粒尺寸小于所述线的剩余部分中所述多个晶粒的标称晶粒尺寸。

公开(公告)号：US08749059B2

公开(公告)日：2014-06-10

申请号：US13418261

申请日：2012-03-12

申请人： Mukta G. Farooq ,  Emily R. Kinser ,  Ian D. Melville ,  Krystyna Waleria Semkow

发明人： Mukta G. Farooq ,  Emily R. Kinser ,  Ian D. Melville ,  Krystyna Waleria Semkow

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L21/02697 ,  H01L23/53238 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0401 ,  H01L2224/05006 ,  H01L2224/05007 ,  H01L2224/05016 ,  H01L2224/05026 ,  H01L2224/05027 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05157 ,  H01L2224/05187 ,  H01L2224/05562 ,  H01L2224/05572 ,  H01L2224/131 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/15787 ,  H01L2924/04953 ,  H01L2924/01014 ,  H01L2224/05552 ,  H01L2924/00

摘要： Disclosed is a process of making a semiconductor device wherein an insulation layer has a copper plug in contact with the last wiring layer of the device. There may also be a barrier layer separating the copper plug from the insulation layer. There may also be a cap layer over the copper plug to protect it from oxidation. There may also be a dielectric layer over the cap layer.

摘要翻译： 公开了制造半导体器件的方法，其中绝缘层具有与器件的最后布线层接触的铜插塞。 还可以存在将铜塞与绝缘层分离的阻挡层。 在铜塞上方也可能有一个盖层，以防止它被氧化。 在盖层上还可以存在介电层。