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23 条记录 (耗时 0.014 秒)

    Internal power voltage generating circuit in semiconductor memory device
    11.
    发明申请
    Internal power voltage generating circuit in semiconductor memory device 有权
    半导体存储器件内部电源电压产生电路

    公开(公告)号：US20070195630A1

    公开(公告)日：2007-08-23

    申请号：US11646543

    申请日：2006-12-28

    申请人： Hyong-Ryol Hwang ,  Ki-Ho Jang

    发明人： Hyong-Ryol Hwang ,  Ki-Ho Jang

    IPC分类号： G11C5/14

    CPC分类号： G11C5/147

    摘要： A method and circuit are disclosed for generating an internal power voltage in a semiconductor memory device. The method includes receiving an external power voltage in an internal power voltage generating circuit and activating a power-up signal during a first period in the applied external power voltage rising to a desired level, powering-up the internal power voltage in relation to the external power voltage during the first period, and continuing the power-up of the internal power voltage during a second period following the first period, the second period extending beyond the deactivation of the power-up signal until receipt of an active command signal.

    摘要翻译： 公开了用于在半导体存储器件中产生内部电源电压的方法和电路。 该方法包括在内部电源电压产生电路中接收外部电源电压，并且在施加的外部电源电压上升至期望电平的第一时段期间激活上电信号，将内部电源电压相对于外部电源 并且在第一周期之后的第二周期期间继续上电内部电源电压，第二周期延长超过上电信号的去激活，直到接收到有效指令信号为止。

    MULTI-PATH ACCESSIBLE SEMICONDUCTOR MEMORY DEVICE HAVING DATA TRANSMISSION MODE BETWEEN PORTS
    12.
    发明申请
    MULTI-PATH ACCESSIBLE SEMICONDUCTOR MEMORY DEVICE HAVING DATA TRANSMISSION MODE BETWEEN PORTS 有权
    具有端口之间的数据传输模式的多通道可访问半导体存储器件

    公开(公告)号：US20070150666A1

    公开(公告)日：2007-06-28

    申请号：US11466406

    申请日：2006-08-22

    申请人： Hyong-Ryol HWANG ,  Sang-Kyun PARK

    发明人： Hyong-Ryol HWANG ,  Sang-Kyun PARK

    IPC分类号： G06F12/00

    CPC分类号： G11C7/1075 ,  G11C8/16

    摘要： A semiconductor memory device including a plurality of ports, at least one shared memory region of a memory cell array accessible through the ports, and a data transmission controller coupled to the shared memory region and the ports. The data transmission controller is configured to apply a read command of a read operation to the shared memory region after a write command of a write operation before applying any other commands to the shared memory region when at least a portion of a write address associated with the write operation and at least a portion of a read address associated with the read operation are substantially equivalent.

    摘要翻译： 一种包括多个端口的半导体存储器件，可通过端口访问的存储器单元阵列的至少一个共享存储器区域，以及耦合到共享存储器区域和端口的数据传输控制器。 所述数据传输控制器被配置为在与所述共享存储器区域相关联的写入地址的至少一部分与所述共享存储器区域相关联的写入地址的至少一部分之前，在写入操作的写入命令之后，向所述共享存储器区域应用读取操作的读取命令 写入操作和与读取操作相关联的读取地址的至少一部分基本相同。

    System and method for performing partial array self-refresh operation in a semiconductor memory device
    13.
    发明申请
    System and method for performing partial array self-refresh operation in a semiconductor memory device 有权
    在半导体存储器件中进行部分阵列自刷新操作的系统和方法

    公开(公告)号：US20050041506A1

    公开(公告)日：2005-02-24

    申请号：US10959804

    申请日：2004-10-06

    申请人： Hyong-Ryol Hwang ,  Jong-Hyun Choi ,  Hyun-Soon Jang

    发明人： Hyong-Ryol Hwang ,  Jong-Hyun Choi ,  Hyun-Soon Jang

    IPC分类号： G11C11/407 ,  G11C7/10 ,  G11C11/403 ,  G11C11/406 ,  G11C11/408 ,  G11C7/00

    CPC分类号： G11C11/40622 ,  G11C7/1018 ,  G11C11/406 ,  G11C11/4087

    摘要： Systems and methods for performing a PASR (partial array self-refresh) operation wherein a refresh operation for recharging stored data is performed on a portion (e.g., ½ ¼, ⅛, or {fraction (1/16)}) of one or more selected memory banks comprising a cell array in a semiconductor memory device. In one aspect, a PASR operation is performed by (1) controlling the generation of row addresses by a row address counter during a self-refresh operation and (2) controlling a self-refresh cycle generating circuit to adjust the self-refresh cycle output therefrom. The self-refresh cycle is adjusted in a manner that provides a reduction in the current dissipation during the PASR operation. In another aspect, a PASR operation is performed by controlling one or more row addresses corresponding to a partial cell array during a self-refresh operation, whereby a reduction in a self-refresh current dissipation is achieved by blocking the activation of a non-used block of a memory bank.

    摘要翻译： 执行PASR（部分阵列自刷新）操作的系统和方法，其中对一个或多个部分（例如，1 / 2,1 / 8或{分数（1/16））的一部分执行用于对存储数据进行再充电的刷新操作 在一个方面，通过（1）在自刷新操作期间通过行地址计数器控制行地址的生成来执行PASR操作，以及（2）控制自身的自身 - 刷新周期产生电路，用于调整其自刷新周期输出，在PASR操作期间以减少电流消耗的方式调整自刷新周期，另一方面，通过控制一个PASR操作来执行PASR操作 或更多行对应于自刷新操作期间的部分单元阵列的行地址，从而通过阻止存储器组的未使用块的激活来实现自刷新电流消耗的减少。

    System and method for performing partial array self-refresh operation in a semiconductor memory device
    14.
    发明授权
    System and method for performing partial array self-refresh operation in a semiconductor memory device 有权
    在半导体存储器件中进行部分阵列自刷新操作的系统和方法

    公开(公告)号：US06590822B2

    公开(公告)日：2003-07-08

    申请号：US09925812

    申请日：2001-08-09

    申请人： Hyong-Ryol Hwang ,  Jong-Hyun Choi ,  Hyun-Soon Jang

    发明人： Hyong-Ryol Hwang ,  Jong-Hyun Choi ,  Hyun-Soon Jang

    IPC分类号： G11C700

    CPC分类号： G11C11/40622 ,  G11C7/1018 ,  G11C11/406 ,  G11C11/4087

    摘要： Systems and methods for performing a PASR (partial array self-refresh) operation wherein a refresh operation for recharging stored data is performed on a portion (e.g., ½ ¼, ⅛, or {fraction (1/16)}) of one or more selected memory banks comprising a cell array in a semiconductor memory device. In one aspect, a PASR operation is performed by (1) controlling the generation of row addresses by a row address counter during a self-refresh operation and (2) controlling a self-refresh cycle generating circuit to adjust the self-refresh cycle output therefrom. The self-refresh cycle is adjusted in a manner that provides a reduction in the current dissipation during the PASR operation. In another aspect, a PASR operation is performed by controlling one or more row addresses corresponding to a partial cell array during a self-refresh operation, whereby a reduction in a self-refresh current dissipation is achieved by blocking the activation of a non-used block of a memory bank.

    摘要翻译： 执行PASR（部分阵列自刷新）操作的系统和方法，其中对一个或多个所选择的存储体的一部分（例如，1/2，1/8或1/16）执行用于对存储的数据进行再充电的刷新操作 包括半导体存储器件中的单元阵列。 一方面，通过以下操作来执行PASR操作：（1）在自刷新操作期间通过行地址计数器控制行地址的生成，以及（2）控制自刷新周期发生电路以调整自刷新周期输出 由此。 调整自刷新周期，从而在PASR操作期间降低电流消耗。 在另一方面，通过在自刷新操作期间控制对应于部分单元阵列的一个或多个行地址来执行PASR操作，由此通过阻止未使用的激活来实现自刷新电流消耗的减少 一块记忆库。

    CONTROL SIGNAL TRANSMITTING SYSTEM OF A SEMICONDUCTOR DEVICE
    17.
    发明申请
    CONTROL SIGNAL TRANSMITTING SYSTEM OF A SEMICONDUCTOR DEVICE 审中-公开
    半导体器件的控制信号传输系统

    公开(公告)号：US20100232213A1

    公开(公告)日：2010-09-16

    申请号：US12711586

    申请日：2010-02-24

    申请人： Hyong-Ryol Hwang ,  Chi-Sung Oh ,  Sang-Kyu Kang

    发明人： Hyong-Ryol Hwang ,  Chi-Sung Oh ,  Sang-Kyu Kang

    IPC分类号： G11C11/24 ,  G11C7/00 ,  G11C8/18

    CPC分类号： G11C7/1048 ,  G11C7/1051 ,  G11C7/1069 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076 ,  G11C11/4091 ,  G11C11/4096

    摘要： Exemplary embodiments relate to a control signal driving device of a semiconductor device, including: a bus line; a converter receiving a first periodic control signal having the period (frequency) of a clock signal, converting the first periodic control signal into a converted control signal that has twice the period (half the frequency) of the clock signal, and outputting the converted control signal to the bus line; and a restoring unit connected to the opposite end of the bus line and receiving the converted control signal and restoring the converted control signal back into the first periodic control signal.

    摘要翻译： 示例性实施例涉及半导体器件的控制信号驱动装置，包括：总线; 接收具有时钟信号的周期（频率）的第一周期性控制信号的转换器，将所述第一周期性控制信号转换成具有所述时钟信号的两倍周期（一半频率）的转换控制信号，并输出所述转换控制 信号到总线; 以及恢复单元，连接到总线的相对端并接收转换的控制信号，并将转换的控制信号恢复到第一周期性控制信号中。

    Device and method for selecting 1-row and 2-row activation
    19.
    发明授权
    Device and method for selecting 1-row and 2-row activation 有权
    用于选择1行和2行激活的设备和方法

    公开(公告)号：US07333387B2

    公开(公告)日：2008-02-19

    申请号：US11428497

    申请日：2006-07-03

    申请人： Hyong-Ryol Hwang

    发明人： Hyong-Ryol Hwang

    IPC分类号： G11C7/00

    CPC分类号： G11C11/4093 ,  G11C7/1045 ,  G11C7/1048 ,  G11C11/4085 ,  G11C2207/002

    摘要： I claim a device and method for selecting 1-row and 2-row activation. A device includes a memory block array including a plurality of memory blocks arranged in a row-column format, a plurality of local inter-connectors to selectively couple upper local lines to lower local lines in corresponding rows of memory blocks and a plurality of local-to-global connection points to selectively couple the upper and lower local lines to one or more global lines in at least an upper left block area and a lower right block area of the memory block array, or in a lower left block area and an upper right block area of the memory block array.

    摘要翻译： 我声称用于选择1行和2行激活的设备和方法。 一种设备包括：存储块阵列，包括以列列格式布置的多个存储块;多个本地互连器，用于选择性地将上部本地线耦合到存储块的相应行中的下部本地线;以及多个本地连接器， 全局连接点，以选择性地将上部和下部本地线耦合到存储器块阵列的至少左上方块区域和右下方块区域中的一个或多个全局线路，或者在左下方区域和上部 内存块阵列的右块区域。