公开(公告)号：US07166540B2

公开(公告)日：2007-01-23

申请号：US11072112

申请日：2005-03-03

Applicant: Nitin A. Deshpande ,  Sandeep B. Sane

Inventor： Nitin A. Deshpande ,  Sandeep B. Sane

IPC: H01L21/31

CPC classification number: H01L21/4882 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/00 ,  H01L2224/0401

Abstract: A method and apparatus for mounting semiconductor die and integral heat spreader are disclosed. In one embodiment, thermal expansion of the integral heat spreader is restricted by physical constraints during the process of heating interface material that bonds the integral heat spreader and semiconductor die together. In an alternative embodiment, thermal expansion of the integral hat spreader is restricted by applying an external compressive force to the integral heat spreader while heating interface material that bonds the integral heat spreader and semiconductor die together.

Abstract translation: 公开了一种用于安装半导体管芯和整体散热器的方法和装置。 在一个实施例中，整体散热器的热膨胀在加热将整体式散热器和半导体管芯结合在一起的界面材料的加工过程中受到物理限制。 在替代实施例中，通过在整体散热器和半导体管芯结合在一起的界面材料的加热的同时，对整体散热器施加外部压缩力来限制整体散热器的热膨胀。

公开(公告)号：US20240006375A1

公开(公告)日：2024-01-04

申请号：US17852992

申请日：2022-06-29

Applicant: Sagar Suthram ,  Wilfred Gomes ,  Pushkar Sharad Ranade ,  Ravindranath Vithal Mahajan ,  Debendra Mallik ,  Omkar G. Karhade ,  Nitin A. Deshpande ,  Abhishek A. Sharma ,  Joshua Fryman ,  Stephen Morein ,  Matthew Adiletta

Inventor： Sagar Suthram ,  Wilfred Gomes ,  Pushkar Sharad Ranade ,  Ravindranath Vithal Mahajan ,  Debendra Mallik ,  Omkar G. Karhade ,  Nitin A. Deshpande ,  Abhishek A. Sharma ,  Joshua Fryman ,  Stephen Morein ,  Matthew Adiletta

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/16 ,  H01L23/48 ,  H01L23/498 ,  H01L23/538 ,  H01L25/00

CPC classification number: H01L25/0652 ,  H01L24/08 ,  H01L24/80 ,  H01L25/167 ,  H01L23/481 ,  H01L23/49811 ,  H01L23/5386 ,  H01L25/50 ,  H01L2224/08121 ,  H01L25/0655 ,  H01L24/16 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2924/1434 ,  H01L2924/1431 ,  H01L2924/3512 ,  H01L2924/3841 ,  H01L2224/08137 ,  H01L2224/08145 ,  H01L2224/08225 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L23/49816 ,  H01L23/5385

Abstract: Embodiments of a microelectronic assembly comprise: a first plurality of integrated circuit (IC) dies coupled on one end to a first IC die and on an opposing end to a second IC die, and a second plurality of IC dies coupled to at least the first IC die or the second IC die. Each IC die in the first plurality of IC dies includes a respective substrate and a respective metallization stack attached along a respective first planar interface, each of the first IC die and the second IC die includes a respective substrate and a respective metallization stack attached along a respective second planar interface, each IC die in the second plurality of IC dies includes a respective substrate and a respective metallization stack attached along a respective third planar interface, and the first planar interface is orthogonal to the second planar interface.

公开(公告)号：US09741692B2

公开(公告)日：2017-08-22

申请号：US14767471

申请日：2014-09-15

Applicant: Omkar G. Karhade ,  Nitin A. Deshpande ,  Edvin Cetegen ,  Eric J. Li ,  Debendra Mallik ,  Bassam M. Ziadeh

Inventor： Omkar G. Karhade ,  Nitin A. Deshpande ,  Edvin Cetegen ,  Eric J. Li ,  Debendra Mallik ,  Bassam M. Ziadeh

IPC: H01L25/00 ,  H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L21/768 ,  H01L25/10 ,  H01L23/498

CPC classification number: H01L25/0657 ,  H01L21/565 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/3142 ,  H01L23/49811 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/1329 ,  H01L2224/133 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81201 ,  H01L2224/81203 ,  H01L2224/81205 ,  H01L2224/81207 ,  H01L2224/81815 ,  H01L2224/83102 ,  H01L2224/92125 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01028 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/1579 ,  H01L2924/1815 ,  H01L2924/01082 ,  H01L2924/0105 ,  H01L2924/00012 ,  H01L2924/01083 ,  H01L2924/01029 ,  H01L2924/00014 ,  H01L2924/0665

Abstract: Methods of fabricating a microelectronic device comprising forming a microelectronic substrate having a plurality microelectronic device attachment bond pads and at least one interconnection bond pad formed in and/or on an active surface thereof, attaching a microelectronic device to the plurality of microelectronic device attachment bond pads, forming a mold chase having a mold body and at least one projection extending from the mold body, wherein the at least one projection includes at least one sidewall and a contact surface, contacting the mold chase projection contact surface to a respective microelectronic substrate interconnection bond pad, disposing a mold material between the microelectronic substrate and the mold chase, and removing the mold chase to form at least one interconnection via extending from a top surface of the mold material to a respective microelectronic substrate interconnection bond pad.

公开(公告)号：US20150279805A1

公开(公告)日：2015-10-01

申请号：US14229788

申请日：2014-03-28

Applicant: Omkar G. KARHADE ,  Nitin A. DESHPANDE, JR. ,  Aditya Sundoctor VAIDYA ,  Nachiket R. RARAVIKAR ,  Eric J. LI

Inventor： Omkar G. KARHADE ,  Nitin A. DESHPANDE, JR. ,  Aditya Sundoctor VAIDYA ,  Nachiket R. RARAVIKAR ,  Eric J. LI

IPC: H01L23/00

CPC classification number: H01L21/565 ,  H01L21/561 ,  H01L21/76879 ,  H01L21/76883 ,  H01L21/78 ,  H01L23/3121 ,  H01L23/49811 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32227 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/83104 ,  H01L2224/83203 ,  H01L2224/83815 ,  H01L2224/92 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2924/0665 ,  H01L21/56 ,  H01L2224/81 ,  H01L2224/45099 ,  H01L2924/00012

Abstract: Embodiments describe a semiconductor package that includes a substrate, a die bonded to the substrate, and a solder paste overmold layer formed over a top surface of the die. In an embodiment, the solder paste comprises a high-melting point metal, a solder matrix, intermetallic compounds and a polymer. The overmold layer has a high elastic modulus, a coefficient of thermal expansion similar to the substrate, and reduces the warpage of the package. In an embodiment, interconnects of a semiconductor package are formed with a no-slump solder paste that includes vents. Vents may be formed through a conductive network formed by the high-melting point metal, solder matrix and intermetallic compounds. In an embodiment, vents provide a path through the interconnect that allows for moisture outgassing. In an embodiment, a mold layer may be mechanically anchored to the interconnects by the vents, thereby providing improved mechanical continuity to the mold layer.

Abstract translation: 实施例描述了一种半导体封装，其包括衬底，结合到衬底的管芯，以及形成在管芯的顶表面上的焊膏二次模制层。 在一个实施例中，焊膏包括高熔点金属，焊料基质，金属间化合物和聚合物。 包覆成型层具有高的弹性模量，类似于基材的热膨胀系数，并且减少了包装的翘曲。 在一个实施例中，半导体封装的互连形成有包括通风口的无洼焊膏。 通孔可以通过由高熔点金属，焊料基质和金属间化合物形成的导电网形成。 在一个实施例中，通风口提供允许湿气除气的互连路径。 在一个实施例中，模具层可以通过通风口机械地锚固到互连，从而提供对模具层的改进的机械连续性。

公开(公告)号：US09123732B2

公开(公告)日：2015-09-01

申请号：US13631612

申请日：2012-09-28

Applicant: Sandeep B. Sane ,  Shankar Ganapathysubramanian ,  Jorge Sanchez ,  Leonel R. Arana ,  Eric J. Li ,  Nitin A. Deshpande ,  Jiraporn Seangatith ,  Poh Chieh Benny Poon

Inventor： Sandeep B. Sane ,  Shankar Ganapathysubramanian ,  Jorge Sanchez ,  Leonel R. Arana ,  Eric J. Li ,  Nitin A. Deshpande ,  Jiraporn Seangatith ,  Poh Chieh Benny Poon

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/00

CPC classification number: H01L24/32 ,  H01L23/562 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/89 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/3213 ,  H01L2224/32225 ,  H01L2224/32501 ,  H01L2224/32505 ,  H01L2224/73253 ,  H01L2224/81007 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/161 ,  H01L2924/16251 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2924/014

Abstract: Die warpage is controlled for the assembly of thin dies. In one example, a device having a substrate on a back side and components in front side layers is formed. A backside layer is formed over the substrate, the layer resisting warpage of the device when the device is heated. The device is attached to a substrate by heating.

Abstract translation: 控制模具翘曲，用于组装薄模具。 在一个示例中，形成具有背面上的基板和在前侧层中的部件的装置。 背衬层形成在衬底上，该层在加热器件时抵抗器件翘曲。 该装置通过加热连接到基板。

公开(公告)号：US07411296B2

公开(公告)日：2008-08-12

申请号：US11394853

申请日：2006-03-13

Applicant: Shubhada H. Sahasrabudhe ,  Nitin A. Deshpande

Inventor： Shubhada H. Sahasrabudhe ,  Nitin A. Deshpande

IPC: H01L23/48

CPC classification number: H01L23/3157 ,  H01L24/03 ,  H01L24/05 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05567 ,  H01L2224/05571 ,  H01L2224/056 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2224/81139 ,  H01L2224/81192 ,  H01L2224/81815 ,  H01L2224/83102 ,  H01L2224/83855 ,  H01L2224/9211 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2224/05552

Abstract: A method, system, and apparatus, the apparatus including a metal layer on silicon, photo-resist material disposed on the metal layer, a bump pad reservoir adjacent to the metal layer, a quantity of interconnect metal disposed in the bump pad reservoir, and a resist opening in resist material disposed on a surface of the bump metal and adjacent the interconnect metal. The resist opening may be wider at an open end thereof than at an end in contact with the interconnect metal.

Abstract translation: 一种方法，系统和装置，所述装置包括硅上的金属层，设置在金属层上的光致抗蚀剂材料，与金属层相邻的凸块焊盘储存器，设置在凸块焊盘储存器中的一定数量的互连金属，以及 抗蚀剂材料中的抗蚀剂开口，设置在凸块金属的表面上且与互连金属相邻。 抗蚀剂开口在其开口端可比在与互连金属接触的端部更宽。