公开(公告)号：US07274106B2

公开(公告)日：2007-09-25

申请号：US10669212

申请日：2003-09-24

Applicant: Sarah E. Kim ,  R. Scott List ,  James G. Maveety ,  Alan M. Myers ,  Quat T. Vu

Inventor： Sarah E. Kim ,  R. Scott List ,  James G. Maveety ,  Alan M. Myers ,  Quat T. Vu

IPC: H01L23/12 ,  H01L23/52 ,  H01L23/48

CPC classification number: H01L23/473 ,  H01L23/34 ,  H01L2224/16 ,  H01L2224/73253 ,  H01L2224/82

Abstract: An integrated electroosmotic pump may be incorporated in the same integrated circuit package with a re-combiner, and an integrated circuit chip to be cooled by fluid pumped by the electroosmotic pump.

Abstract translation: 集成电渗泵可以结合在具有再组合器的相同的集成电路封装中，以及通过由电渗泵泵送的流体冷却的集成电路芯片。

公开(公告)号：US07056813B2

公开(公告)日：2006-06-06

申请号：US11071434

申请日：2005-03-02

Applicant: Patrick Morrow ,  R. Scott List ,  Sarah E. Kim

Inventor： Patrick Morrow ,  R. Scott List ,  Sarah E. Kim

IPC: H01L21/30

CPC classification number: H01L25/50 ,  H01L21/76898 ,  H01L23/481 ,  H01L25/0657 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/13025 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/2919 ,  H01L2224/8182 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/01079 ,  H01L2924/00014 ,  H01L2924/01082

Abstract: Various methods of forming backside connections on a wafer stack are disclosed. To form the backside connections, vias are formed in a first wafer that is to be bonded with a second wafer. The vias used for the backside connections are formed on a side of the first wafer along with an interconnect structure, and the backside connections are formed on an opposing side of the first wafer using these vias.

Abstract translation: 公开了在晶片叠层上形成背面连接的各种方法。 为了形成背面连接，通孔形成在要与第二晶片结合的第一晶片中。 用于背面连接的通路与互连结构一起形成在第一晶片的一侧，并且使用这些通孔在第一晶片的相对侧上形成背面连接。

公开(公告)号：US06981849B2

公开(公告)日：2006-01-03

申请号：US10323084

申请日：2002-12-18

Applicant: Sarah E. Kim ,  R. Scott List ,  James Maveety ,  Alan Myers ,  Quat T. Vu ,  Ravi Prasher ,  Ravindranath V. Mahajan

Inventor： Sarah E. Kim ,  R. Scott List ,  James Maveety ,  Alan Myers ,  Quat T. Vu ,  Ravi Prasher ,  Ravindranath V. Mahajan

IPC: F04B44/08

CPC classification number: F04B19/006 ,  H01L23/473 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present disclosure relates generally to microelectronic technology, and more specifically, to an apparatus used for the cooling of active electronic devices utilizing electro-osmotic pumps and micro-channels.

Abstract translation: 本公开一般涉及微电子技术，更具体地，涉及使用电渗透泵和微通道来冷却有源电子器件的装置。

公开(公告)号：US06977435B2

公开(公告)日：2005-12-20

申请号：US10659044

申请日：2003-09-09

Applicant: Sarah E. Kim ,  Bob Martell ,  Dave Ayers ,  R. Scott List ,  Peter Moon ,  Anna M. George, legal representative

Inventor： Steven Towle, deceased

IPC: H01L21/60 ,  H01L21/768 ,  H01L23/36 ,  H01L23/485 ,  H01L23/498 ,  H01L23/528 ,  H01L23/532 ,  H01L29/40

CPC classification number: H01L24/12 ,  H01L21/76838 ,  H01L23/36 ,  H01L23/49816 ,  H01L23/5283 ,  H01L23/5286 ,  H01L23/53238 ,  H01L24/11 ,  H01L24/16 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05572 ,  H01L2224/05666 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15312 ,  H01L2924/16152 ,  H01L2924/19043 ,  H01L2924/3011 ,  H01L2924/00014

Abstract: A process flow to make an interconnect structure with one or more thick metal layers under Controlled Collapse Chip Connection (C4) bumps at a die or wafer level. The interconnect structure may be used in a backend interconnect of a microprocessor. The one or more integrated thick metal layers may improve power delivery and reduce mechanical stress to a die at a die/package interface.

Abstract translation: 在芯片或晶片级别的受控崩溃芯片连接（C4）凸起处形成具有一个或多个厚金属层的互连结构的工艺流程。 互连结构可以用在微处理器的后端互连中。 一个或多个集成的厚金属层可以改善功率传递并且降低在管芯/封装接口处的管芯的机械应力。

公开(公告)号：US06975016B2

公开(公告)日：2005-12-13

申请号：US10066643

申请日：2002-02-06

Applicant: Scot A. Kellar ,  Sarah E. Kim ,  R. Scott List

Inventor： Scot A. Kellar ,  Sarah E. Kim ,  R. Scott List

IPC: H01L21/18 ,  H01L21/74 ,  H01L21/768 ,  H01L23/48 ,  H01L25/065 ,  H01L29/06 ,  G01R1/073 ,  B23K19/00

CPC classification number: H01L25/50 ,  H01L21/185 ,  H01L21/743 ,  H01L21/76898 ,  H01L24/12 ,  H01L24/16 ,  H01L24/72 ,  H01L24/75 ,  H01L25/0657 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/13099 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13166 ,  H01L2224/16 ,  H01L2224/2919 ,  H01L2224/75315 ,  H01L2224/81203 ,  H01L2224/81894 ,  H01L2224/81895 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/04941 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/30107 ,  H01L2924/0665 ,  H01L2924/00014

Abstract: A three-dimensional (3-D) integrated chip system is provided with a first wafer including one or more integrated circuit (IC) devices; a second wafer including one or more integrated circuit (IC) devices; and a metal bonding layer deposited on opposing surfaces of the first and second wafers at designated locations to establish electrical connections between active IC devices on the first and second wafers and to provide metal bonding between the adjacent first and second wafers, when the first wafer is pressed against the second wafer using a flexible bladder press to account for height differences of the metal bonding layer across the opposing surfaces of the first and second wafers.

Abstract translation: 三维（3-D）集成芯片系统设置有包括一个或多个集成电路（IC）装置的第一晶片; 包括一个或多个集成电路（IC）装置的第二晶片; 以及在指定位置沉积在第一和第二晶片的相对表面上的金属粘结层，以在第一和第二晶片上的有源IC器件之间建立电连接，并且当第一晶片为 使用柔性膀胱压力机压在第二晶片上，以考虑穿过第一和第二晶片的相对表面的金属粘合层的高度差异。

公开(公告)号：US06664168B1

公开(公告)日：2003-12-16

申请号：US10202807

申请日：2002-07-24

Applicant: Ebrahim Andideh ,  R. Scott List

Inventor： Ebrahim Andideh ,  R. Scott List

IPC: H01L2120

CPC classification number: H01L28/55

Abstract: A method of making an on-die decoupling capacitor for a semiconductor device is described. That method comprises forming a first barrier layer on a conductive layer. The upper surface of the first barrier layer is modified to enable a dielectric layer with an acceptable nucleation density to be formed on the first barrier layer. A dielectric layer is formed on the first barrier layer, and a second barrier layer is formed on the dielectric layer.

Abstract translation: 描述了制造用于半导体器件的芯片上去耦电容器的方法。 该方法包括在导电层上形成第一阻挡层。 修改第一阻挡层的上表面以使得能够在第一阻挡层上形成具有可接受的成核密度的介电层。 在第一阻挡层上形成电介质层，在电介质层上形成第二阻挡层。

公开(公告)号：US07842553B2

公开(公告)日：2010-11-30

申请号：US11796235

申请日：2007-04-27

Applicant: Sarah E. Kim ,  R. Scott List ,  Alan Myers

Inventor： Sarah E. Kim ,  R. Scott List ,  Alan Myers

IPC: H01L21/00 ,  H01L23/34

CPC classification number: H01L23/473 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present disclosure relates generally to microelectronic technology, and more specifically, to an apparatus used for the cooling of active electronic devices utilizing micro-channels or micro-trenches, and a technique for fabricating the same.

Abstract translation: 本公开一般涉及微电子技术，更具体地，涉及用于利用微通道或微沟槽冷却有源电子器件的装置及其制造技术。

公开(公告)号：US07576432B2

公开(公告)日：2009-08-18

申请号：US11270071

申请日：2005-11-09

Applicant: Sarah E. Kim ,  R. Scott List ,  James G. Maveety ,  Alan M. Myers ,  Quat T. Vu ,  Ravi Prasher ,  Ravi Mahajan ,  Gilroy Vandentop

Inventor： Sarah E. Kim ,  R. Scott List ,  James G. Maveety ,  Alan M. Myers ,  Quat T. Vu ,  Ravi Prasher ,  Ravi Mahajan ,  Gilroy Vandentop

IPC: H01L23/52 ,  H01L23/48 ,  H01L29/40

CPC classification number: H01L23/473 ,  H01L2224/16 ,  H01L2224/73253 ,  H01L2224/82

Abstract: An integrated circuit to be cooled may be abutted in face-to-face abutment with a cooling integrated circuit. The cooling integrated circuit may include electroosmotic pumps to pump cooling fluid through the cooling integrated circuits via microchannels to thereby cool the heat generating integrated circuit. The electroosmotic pumps may be fluidically coupled to external radiators which extend upwardly away from a package including the integrated circuits. In particular, the external radiators may be mounted on tubes which extend the radiators away from the package.

Abstract translation: 要冷却的集成电路可以与冷却集成电路面对面邻接。 冷却集成电路可以包括电渗泵，以通过微通道将冷却流体泵送通过冷却集成电路，从而冷却发热集成电路。 电渗泵可以流体耦合到从包括集成电路的包装向上延伸的外部散热器。 特别地，外部散热器可以安装在使散热器远离封装的管上。

公开(公告)号：US07569426B2

公开(公告)日：2009-08-04

申请号：US11691124

申请日：2007-03-26

Applicant: Alan M. Myers ,  R. Scott List ,  Gilroy J. Vandentop

Inventor： Alan M. Myers ,  R. Scott List ,  Gilroy J. Vandentop

IPC: H01L21/00

CPC classification number: H01L23/473 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/00

Abstract: A die package and a method and apparatus for integrating an electro-osmotic pump and a microchannel cooling assembly into a die package.

Abstract translation: 一种模具封装以及用于将电渗透泵和微通道冷却组件集成到管芯封装中的方法和装置。

公开(公告)号：US07355277B2

公开(公告)日：2008-04-08

申请号：US10750224

申请日：2003-12-31

Applicant: Alan M. Myers ,  R. Scott List ,  Gilroy J. Vandentop

Inventor： Alan M. Myers ,  R. Scott List ,  Gilroy J. Vandentop

IPC: H01L23/34

CPC classification number: H01L23/473 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/00

Abstract: A die package and a method and apparatus for integrating an electro-osmotic pump and a microchannel cooling assembly into a die package.

Abstract translation: 一种模具封装以及用于将电渗透泵和微通道冷却组件集成到管芯封装中的方法和装置。