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公开(公告)号：US11957065B2
公开(公告)日：2024-04-09
申请号：US17321819
申请日：2021-05-17
Applicant: D-WAVE SYSTEMS INC.
Inventor： Shuiyuan Huang , Byong H. Oh , Douglas P. Stadtler , Edward G. Sterpka , Paul I. Bunyk , Jed D. Whittaker , Fabio Altomare , Richard G. Harris , Colin C. Enderud , Loren J. Swenson , Nicolas C. Ladizinsky , Jason J. Yao , Eric G. Ladizinsky
IPC: H10N60/01 , H01L21/768 , H01L23/522 , H01L23/528 , H01L23/532 , H10N60/85 , H10N69/00
CPC classification number: H10N60/0156 , H01L21/76891 , H01L23/5223 , H01L23/5226 , H01L23/5227 , H01L23/528 , H01L23/53257 , H01L23/53285 , H10N60/85 , H10N69/00
Abstract: Various techniques and apparatus permit fabrication of superconductive circuits. A superconducting integrated circuit comprising a superconducting stud via, a kinetic inductor, and a capacitor may be formed. Forming a superconducting stud via in a superconducting integrated circuit may include masking with a hard mask and masking with a soft mask. Forming a superconducting stud via in a superconducting integrated circuit may include depositing a dielectric etch stop layer. Interlayer misalignment in the fabrication of a superconducting integrated circuit may be measured by an electrical vernier. Interlayer misalignment in the fabrication of a superconducting integrated circuit may be measured by a chain of electrical verniers and a Wheatstone bridge. A superconducting integrated circuit with three or more metal layers may include an enclosed, matched, on-chip transmission line. A metal wiring layer in a superconducting integrated circuit may be encapsulated.
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12.发明授权公开(公告)号：US11797874B2
公开(公告)日：2023-10-24
申请号：US17387654
申请日：2021-07-28
Applicant: D-WAVE SYSTEMS INC.
Inventor： Paul I. Bunyk , James King , Murray C. Thom , Mohammad H. Amin , Anatoly Smirnov , Sheir Yarkoni , Trevor M. Lanting , Andrew D. King , Kelly T. R. Boothby
CPC classification number: G06N10/00 , G06F11/0736 , G06F11/0751 , G06F11/0793
Abstract: The systems, devices, articles, and methods described herein generally relate to analog computers, for example quantum processors comprising qubits, couplers, and, or cavities. Analog computers, for example quantum processor based computers, are the subject of various sources of error which can hinder operation, potentially reducing computational accuracy and speed. Sources of error can be broadly characterized, for example as i) a background susceptibility do to inherently characteristics of the circuitry design, ii) as an h/J ratio imbalance, iii) bit flip errors, iv) fidelity, and v) Anderson localization, and various combinations of the aforesaid.
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公开(公告)号：US11038095B2
公开(公告)日：2021-06-15
申请号：US16481788
申请日：2018-01-31
Applicant: D-WAVE SYSTEMS INC.
Inventor： Shuiyuan Huang , Byong H. Oh , Douglas P. Stadtler , Edward G. Sterpka , Paul I. Bunyk , Jed D. Whittaker , Fabio Altomare , Richard G. Harris , Colin C. Enderud , Loren J. Swenson , Nicolas C. Ladizinsky , Jason J. Yao , Eric G. Ladizinsky
IPC: H01L27/18 , H01L39/24 , H01L21/768 , H01L23/522 , H01L23/528 , H01L23/532 , H01L39/12
Abstract: Various techniques and apparatus permit fabrication of superconductive circuits. A superconducting integrated circuit comprising a superconducting stud via, a kinetic inductor, and a capacitor may be formed. Forming a superconducting stud via in a superconducting integrated circuit may include masking with a hard mask and masking with a soft mask. Forming a superconducting stud via in a superconducting integrated circuit may include depositing a dielectric etch stop layer. Interlayer misalignment in the fabrication of a superconducting integrated circuit may be measured by an electrical vernier. Interlayer misalignment in the fabrication of a superconducting integrated circuit may be measured by a chain of electrical verniers and a Wheatstone bridge. A superconducting integrated circuit with three or more metal layers may include an enclosed, matched, on-chip transmission line. A metal wiring layer in a superconducting integrated circuit may be encapsulated.
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公开(公告)号：US10938346B2
公开(公告)日：2021-03-02
申请号：US15572731
申请日：2016-05-11
Applicant: D-Wave Systems Inc.
Inventor： Andrew J. Berkley , Loren J. Swenson , Mark H. Volkmann , Jed D. Whittaker , Paul I. Bunyk , Peter D. Spear , Christopher B. Rich
Abstract: A superconducting input and/or output system employs at least one microwave superconducting resonator. The microwave superconducting resonator(s) may be communicatively coupled to a microwave transmission line. Each microwave superconducting resonator may include a first and a second DC SQUID, in series with one another and with an inductance (e.g., inductor), and a capacitance in parallel with the first and second DC SQUIDs and inductance. Respective inductive interfaces are operable to apply flux bias to control the DC SQUIDs. The second DC SQUID may be coupled to a Quantum Flux Parametron (QFP), for example as a final element in a shift register. A superconducting parallel plate capacitor structure and method of fabricating such are also taught.
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公开(公告)号：US20190305206A1
公开(公告)日：2019-10-03
申请号：US16380751
申请日：2019-04-10
Applicant: D-WAVE SYSTEMS INC.
Inventor： Richard G. Harris , Andrew J. Berkley , Jan Johansson , Mark Johnson , Mohammad Amin , Paul I. Bunyk
Abstract: Apparatus and methods enable active compensation for unwanted discrepancies in the superconducting elements of a quantum processor. A qubit may include a primary compound Josephson junction (CJJ) structure, which may include at least a first secondary CJJ structure to enable compensation for Josephson junction asymmetry in the primary CJJ structure. A qubit may include a series LC-circuit coupled in parallel with a first CJJ structure to provide a tunable capacitance. A qubit control system may include means for tuning inductance of a qubit loop, for instance a tunable coupler inductively coupled to the qubit loop and controlled by a programming interface, or a CJJ structure coupled in series with the qubit loop and controlled by a programming interface.
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Patent Agency Ranking
公开(公告)号：US10290798B2
公开(公告)日：2019-05-14
申请号：US15438296
申请日：2017-02-21
Applicant: D-Wave Systems Inc.
Inventor： Richard G. Harris , Andrew J. Berkley , Jan Johansson , Mark Johnson , Mohammad Amin , Paul I. Bunyk
Abstract: Apparatus and methods enable active compensation for unwanted discrepancies in the superconducting elements of a quantum processor. A qubit may include a primary compound Josephson junction (CJJ) structure, which may include at least a first secondary CJJ structure to enable compensation for Josephson junction asymmetry in the primary CJJ structure. A qubit may include a series LC-circuit coupled in parallel with a first CJJ structure to provide a tunable capacitance. A qubit control system may include means for tuning inductance of a qubit loop, for instance a tunable coupler inductively coupled to the qubit loop and controlled by a programming interface, or a CJJ structure coupled in series with the qubit loop and controlled by a programming interface.
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公开(公告)号：US10140248B2
公开(公告)日：2018-11-27
申请号：US15635735
申请日：2017-06-28
Applicant: D-Wave Systems Inc.
Inventor： Alexander Maassen van den Brink , Peter Love , Mohammad H. S. Amin , Geordie Rose , David Grant , Miles F. H. Steininger , Paul I. Bunyk , Andrew J. Berkley
Abstract: Analog processors for solving various computational problems are provided. Such analog processors comprise a plurality of quantum devices, arranged in a lattice, together with a plurality of coupling devices. Such quantum processors further comprise a set of readout devices each configured to measure the information from a corresponding quantum device in the plurality of quantum devices. A method of determining a result of a computational problem using an analog processor includes receiving at a first digital computer, including a digital processor, an instance of the computational problem defined over an input graph, wherein the input graph is non-planar; and determining a mapping of the instance of the computational problem onto the analog processor, by the digital processor.
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公开(公告)号：US20180033944A1
公开(公告)日：2018-02-01
申请号：US15679963
申请日：2017-08-17
Applicant: D-WAVE SYSTEMS INC.
Inventor： Eric Ladizinsky , Jeremy P. Hilton , Byong Hyop Oh , Paul I. Bunyk
CPC classification number: H01L39/2493 , B82Y10/00 , G06N10/00 , H01L21/2855 , H01L21/76877 , H01L21/76891 , H01L27/18 , H01L39/025 , H01L39/125 , H01L39/22 , H01L39/223 , H01L39/24 , H01L39/2406
Abstract: Various techniques and apparatus permit fabrication of superconductive circuits. A niobium/aluminum oxide/niobium trilayer may be formed and individual Josephson Junctions (JJs) formed. A protective cap may protect a JJ during fabrication. A hybrid dielectric may be formed. A superconductive integrated circuit may be formed using a subtractive patterning and/or additive patterning. A superconducting metal layer may be deposited by electroplating and/or polished by chemical-mechanical planarization. The thickness of an inner layer dielectric may be controlled by a deposition process. A substrate may include a base of silicon and top layer including aluminum oxide. Depositing of superconducting metal layer may be stopped or paused to allow cooling before completion. Multiple layers may be aligned by patterning an alignment marker in a superconducting metal layer.
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公开(公告)号：US20170300454A1
公开(公告)日：2017-10-19
申请号：US15635735
申请日：2017-06-28
Applicant: D-Wave Systems Inc.
Inventor： Alexander Maassen van den Brink , Peter Love , Mohammad H.S. Amin , Geordie Rose , David Grant , Miles F.H. Steininger , Paul I. Bunyk , Andrew J. Berkley
Abstract: Analog processors for solving various computational problems are provided. Such analog processors comprise a plurality of quantum devices, arranged in a lattice, together with a plurality of coupling devices. The analog processors further comprise bias control systems each configured to apply a local effective bias on a corresponding quantum device. A set of coupling devices in the plurality of coupling devices is configured to couple nearest-neighbor quantum devices in the lattice. Another set of coupling devices is configured to couple next-nearest neighbor quantum devices. The analog processors further comprise a plurality of coupling control systems each configured to tune the coupling value of a corresponding coupling device in the plurality of coupling devices to a coupling. Such quantum processors further comprise a set of readout devices each configured to measure the information from a corresponding quantum device in the plurality of quantum devices.
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公开(公告)号：US09768371B2
公开(公告)日：2017-09-19
申请号：US14383837
申请日：2013-03-07
Applicant: D-Wave Systems Inc.
Inventor： Eric Ladizinsky , Jeremy P. Hilton , Byong Hyop Oh , Paul I. Bunyk
CPC classification number: H01L39/2493 , B82Y10/00 , G06N99/002 , H01L27/18 , H01L39/025 , H01L39/125 , H01L39/22 , H01L39/223 , H01L39/24 , H01L39/2406
Abstract: Various techniques and apparatus permit fabrication of superconductive circuits. A niobium/aluminum oxide/niobium trilayer may be formed and individual Josephson Junctions (JJs) formed. A protective cap may protect a JJ during fabrication. A hybrid dielectric may be formed. A superconductive integrated circuit may be formed using a subtractive patterning and/or additive patterning. A superconducting metal layer may be deposited by electroplating and/or polished by chemical-mechanical planarization. The thickness of an inner layer dielectric may be controlled by a deposition process. A substrate may include a base of silicon and top layer including aluminum oxide. Depositing of superconducting metal layer may be stopped or paused to allow cooling before completion. Multiple layers may be aligned by patterning an alignment marker in a superconducting metal layer.
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