公开(公告)号：US10032910B2

公开(公告)日：2018-07-24

申请号：US14695411

申请日：2015-04-24

Applicant: GLOBALFOUNDRIES, INC.

Inventor： Xusheng Wu ,  Changyong Xiao ,  Min-hwa Chi

IPC: H01L29/78 ,  H01L29/08 ,  H01L27/088 ,  H01L29/66 ,  H01L21/3115 ,  H01L29/165

Abstract: Fin field-effect transistor (FinFET) devices and methods of forming the same are provided herein. In an embodiment, a FinFET device includes a semiconductor substrate having a plurality of fins disposed in parallel relationship. A first insulator layer overlies the semiconductor substrate, with the fins extending through and protruding beyond the first insulator layer to provide exposed fin portions. A gate electrode structure overlies the exposed fin portions and is electrically insulated from the fins by a gate insulating layer. Epitaxially-grown source regions and drain regions are disposed adjacent to the gate electrode structure. The epitaxially-grown source regions and drain regions have an asymmetric profile along a lateral direction perpendicular to a length of the fins.

公开(公告)号：US20160315172A1

公开(公告)日：2016-10-27

申请号：US14695411

申请日：2015-04-24

Applicant: GLOBALFOUNDRIES, INC.

Inventor： Xusheng Wu ,  Changyong Xiao ,  Min-hwa Chi

IPC: H01L29/66 ,  H01L27/088 ,  H01L29/78 ,  H01L29/08

CPC classification number: H01L29/7848 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31155 ,  H01L27/0886 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/66795

Abstract: Fin field-effect transistor (FinFET) devices and methods of forming the same are provided herein. In an embodiment, a FinFET device includes a semiconductor substrate having a plurality of fins disposed in parallel relationship. A first insulator layer overlies the semiconductor substrate, with the fins extending through and protruding beyond the first insulator layer to provide exposed fin portions. A gate electrode structure overlies the exposed fin portions and is electrically insulated from the fins by a gate insulating layer. Epitaxially-grown source regions and drain regions are disposed adjacent to the gate electrode structure. The epitaxially-grown source regions and drain regions have an asymmetric profile along a lateral direction perpendicular to a length of the fins.

Abstract translation: Fin场效应晶体管（FinFET）器件及其形成方法在此提供。 在一个实施例中，FinFET器件包括具有平行关系设置的多个鳍片的半导体衬底。 第一绝缘体层覆盖在半导体衬底上，鳍片延伸穿过第一绝缘体层并突出超过第一绝缘体层以提供暴露的鳍部分。 栅电极结构覆盖在暴露的鳍部上，并通过栅极绝缘层与散热片电绝缘。 外延生长的源极区域和漏极区域邻近栅电极结构设置。 外延生长的源极区域和漏极区域沿着垂直于鳍片的长度的横向方向具有不对称轮廓。

公开(公告)号：US09362284B2

公开(公告)日：2016-06-07

申请号：US14924486

申请日：2015-10-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Mitsuhiro Togo ,  Changyong Xiao ,  Yiqun Liu ,  Dina H. Triyoso ,  Rohit Pal

IPC: H01L29/00 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/324 ,  H01L21/265 ,  H01L21/321 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/84 ,  H01L29/417 ,  H01L29/49

CPC classification number: H01L27/0922 ,  H01L21/26513 ,  H01L21/32115 ,  H01L21/324 ,  H01L21/823431 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/845 ,  H01L27/0924 ,  H01L29/41791 ,  H01L29/49 ,  H01L29/4958 ,  H01L29/66545 ,  H01L29/66795

Abstract: A range of lowest, low and regular threshold voltages are provided to three p-type devices and three n-type devices co-fabricated on a same substrate. For the p-type devices, the range is achieved for the lowest using an additional thick layer of a p-type work function metal in a gate structure and oxidizing it, the low Vt is achieved with the thick p-type work function metal alone, and the regular Vt is achieved with a thinner layer of the p-type work function metal. For the n-type devices, the lowest Vt is achieved by implanting tantalum nitride with arsenic, argon, silicon or germanium and not adding any of the additional p-type work function metal in the gate structure, the low Vt is achieved by not adding the additional p-type work function metal, and the regular Vt is achieved with a thinnest layer of the p-type work function metal.

公开(公告)号：US09159567B1

公开(公告)日：2015-10-13

申请号：US14259497

申请日：2014-04-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Changyong Xiao ,  Hoong Shing Wong ,  Deepasree Konduparthi ,  Rohit Pal

IPC: H01L21/336 ,  H01L21/28

CPC classification number: H01L29/6653 ,  H01L21/823842 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/7842

Abstract: A method includes providing a gate structure having a dummy gate, a first spacer along a side of the gate. The dummy gate and the spacer are removed to expose a gate dielectric. A second spacer is deposited on at least one side of a gate structure cavity and a top of the gate dielectric. A bottom portion of the second spacer is removed to expose the gate dielectric and the gate structure is wet cleaned.

Abstract translation: 一种方法包括提供具有虚拟栅极的栅极结构，沿栅极侧面的第一间隔物。 去除虚拟栅极和间隔物以露出栅极电介质。 第二间隔物沉积在栅极结构腔的至少一侧和栅极电介质的顶部。 去除第二间隔件的底部以暴露栅极电介质，并且将栅极结构湿式清洁。

公开(公告)号：US20140131881A1

公开(公告)日：2014-05-15

申请号：US13673549

申请日：2012-11-09

Applicant: GLOBALFOUNDRIES INC.

Inventor： Xin Wang ,  Changyong Xiao ,  Yue Hu ,  Yong Meng Lee ,  Meng Luo ,  Jialin Weng ,  Wei Hua Tong ,  Wen-Pin Peng

IPC: H01L23/48 ,  H01L21/20 ,  H01L21/768

CPC classification number: H01L21/76846 ,  H01L21/28518 ,  H01L21/76814 ,  H01L21/76831 ,  H01L21/76844

Abstract: Integrated circuits and methods of forming integrated circuits are provided herein. In an embodiment, a method of forming an integrated circuit includes providing a base substrate having an embedded electrical contact disposed therein. An interlayer dielectric is formed overlying the base substrate, and a recess is etched through the interlayer dielectric over the embedded electrical contact. A protecting liner is formed in the recess and over an exposed surface of the embedded electrical contact in the recess. The protecting liner includes at least two liner layers that have materially different etch rates in different etchants. A portion of the protecting liner is removed over the surface of the embedded electrical contact to again expose the surface of the embedded electrical contact in the recess. An embedded electrical interconnect is formed in the recess. The embedded electrical interconnect overlies the protecting liner on sides of the recess.

Abstract translation: 本文提供集成电路和形成集成电路的方法。 在一个实施例中，形成集成电路的方法包括提供其中布置有嵌入式电触头的基底基板。 在基底基板上形成层间电介质，通过嵌入的电触头上的层间电介质蚀刻凹陷。 保护衬垫形成在凹部中并且在凹部中的嵌入式电触点的暴露表面上。 保护衬垫包括至少两个衬垫层，其在不同的蚀刻剂中具有实质上不同的蚀刻速率。 保护衬垫的一部分在嵌入的电触点的表面上被去除，以再次暴露凹陷中嵌入的电触点的表面。 在凹部中形成嵌入式电气互连。 嵌入式电互连覆盖在凹槽侧面上的保护衬垫。

公开(公告)号：US08617996B1

公开(公告)日：2013-12-31

申请号：US13738435

申请日：2013-01-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Min-hwa Chi ,  Honglian Shen ,  Changyong Xiao

IPC: H01L21/311

CPC classification number: H01L21/30604 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/823431 ,  H01L21/823821

Abstract: Methods for removal of fins from a semiconductor structure are provided. A fin liner is applied to the fins. The fin liner is then removed from the fins that are to be removed. The fin liner is of a material that is selective compared to the semiconductor fins. Hence, the fins can be removed without significant damage to the fin liner. The subsets of fins that are to be removed are then removed, while the fin liner protects the adjacent fins that are to be kept.

Abstract translation: 提供了从半导体结构中去除散热片的方法。 翅片衬垫应用于翅片。 然后将翅片衬垫从要去除的翅片上移除。 翅片衬套是与半导体翅片相比是选择性的材料。 因此，可以去除翅片而不会对翼片衬垫造成显着损坏。 然后去除要去除的翅片的子集，而翅片衬垫保护待保持的相邻翅片。

公开(公告)号：US09419015B1

公开(公告)日：2016-08-16

申请号：US14656758

申请日：2015-03-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xusheng Wu ,  Changyong Xiao ,  Min-hwa Chi

IPC: H01L27/12 ,  H01L21/84 ,  H01L21/265 ,  H01L29/66 ,  H01L29/06 ,  H01L21/266 ,  H01L29/78 ,  H01L29/786 ,  H01L21/8234 ,  H01L27/06 ,  H01L27/088

CPC classification number: H01L27/1207 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/823412 ,  H01L21/84 ,  H01L27/0617 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/66757 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/78675

Abstract: Methods for integrating core and I/O components in IC devices utilizing a TFT I/O device formed on STI regions, and the resulting devices are disclosed. Embodiments include forming STI and FinFET regions in a Si substrate, the FinFET region having first and second adjacent sections; forming a nitride layer and a silicon layer, respectively, over the STI region and both sections of the FinFET region; removing a first section of the silicon and nitride layers through a mask to expose the first FinFET section; implanting the exposed FinFET section with a dopant; removing remaining sections of the mask; removing a second section of the silicon and nitride layers through a second mask to expose the second FinFET section; implanting the second FinFET section with another dopant; removing remaining sections of the second mask; and forming a TFT on the remaining silicon layer, wherein the TFT channel includes the silicon layer.

Abstract translation: 公开了利用在STI区域上形成的TFT I / O装置的集成电路装置中的核心和I / O部件的集成方法。 实施例包括在Si衬底中形成STI和FinFET区域，FinFET区域具有第一和第二相邻区段; 分别在STI区域和FinFET区域的两个部分上形成氮化物层和硅层; 通过掩模去除所述硅和氮化物层的第一部分以暴露所述第一FinFET部分; 用掺杂剂注入暴露的FinFET部分; 去除面罩的剩余部分; 通过第二掩模去除所述硅和氮化物层的第二部分以暴露所述第二FinFET部分; 用另一个掺杂剂注入第二FinFET部分; 去除所述第二掩模的剩余部分; 以及在剩余硅层上形成TFT，其中TFT沟道包括硅层。

公开(公告)号：US09275906B2

公开(公告)日：2016-03-01

申请号：US14267611

申请日：2014-05-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xusheng Wu ,  Xiang Hu ,  Changyong Xiao ,  Wanxun He

IPC: H01L21/8238 ,  H01L21/306 ,  H01L21/02 ,  H01L27/092 ,  H01L29/161 ,  H01L29/16 ,  H01L29/201

CPC classification number: H01L29/0657 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/02546 ,  H01L21/0259 ,  H01L21/02639 ,  H01L21/02664 ,  H01L21/30604 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/0922 ,  H01L27/0924 ,  H01L29/0692 ,  H01L29/16 ,  H01L29/161 ,  H01L29/20 ,  H01L29/201

Abstract: A non-planar semiconductor structure includes mixed n-and-p type raised semiconductor structures, e.g., fins, having epitaxial structures grown on top surfaces thereof, for example, epitaxial silicon and silicon germanium, naturally growing into a diamond shape. The surface area of the epitaxial structures is increased by removing portion(s) thereof, masking each type as the other type is grown and then subsequently modified by the removal. The removal may create multi-head (e.g., dual-head) epitaxial structures, together with the neck of the respective raised structure resembling a Y-shape.

Abstract translation: 非平面半导体结构包括混合的n型和p型凸起半导体结构，例如具有在其顶表面上生长的外延结构的散热片，例如外延硅和硅锗，天然生长成菱形。 外延结构的表面积通过去除其部分而增加，当另一种类型生长然后随后通过去除而修饰时，掩蔽每种类型。 移除可以与类似于Y形的相应凸起结构的颈部一起产生多头（例如，双头）外延结构。

公开(公告)号：US09263516B1

公开(公告)日：2016-02-16

申请号：US14823319

申请日：2015-08-11

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xusheng Wu ,  Changyong Xiao ,  Wanxun He ,  Hongliang Shen

IPC: H01L21/84 ,  H01L21/00 ,  H01L29/66 ,  H01L29/06 ,  H01L27/088

CPC classification number: H01L29/0646 ,  H01L21/76224 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0653

Abstract: An integrated circuit product is disclosed that includes a plurality of trenches in a semiconducting substrate that define first, second and third fins, wherein the fins are side-by-side, and wherein the second fin is positioned between the first and third fins, a layer of insulating material in the plurality of trenches such that a desired height of the first, second and third fins is positioned above an upper surface of the layer of insulating material, a recess defined in the second fin that at least partially defines a cavity in the layer of insulating material, an SDB isolation structure in the cavity on the recessed portion of the second fin, wherein the SDB isolation structure has an upper surface that is above the upper surface of the layer of insulating material, and a gate structure for a transistor positioned above the SDB isolation structure.

Abstract translation: 公开了一种集成电路产品，其包括限定第一，第二和第三鳍片的半导体衬底中的多个沟槽，其中散热片并排，并且其中第二鳍片位于第一和第三鳍片之间， 多个沟槽中的绝缘材料层，使得第一，第二和第三鳍片的期望高度位于绝缘材料层的上表面上方，限定在第二鳍片中的凹部，其至少部分地限定在第 所述绝缘材料层，在所述第二鳍片的凹陷部分上的空腔中的SDB隔离结构，其中所述SDB隔离结构具有位于所述绝缘材料层的上表面上方的上表面，以及用于 晶体管位于SDB隔离结构之上。

公开(公告)号：US09123783B2

公开(公告)日：2015-09-01

申请号：US13673549

申请日：2012-11-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xin Wang ,  Changyong Xiao ,  Yue Hu ,  Yong Meng Lee ,  Meng Luo ,  Jialin Weng ,  Wei Hua Tong ,  Wen-Pin Peng

IPC: H01L21/44 ,  H01L21/768 ,  H01L21/285

CPC classification number: H01L21/76846 ,  H01L21/28518 ,  H01L21/76814 ,  H01L21/76831 ,  H01L21/76844

Abstract: Integrated circuits and methods of forming integrated circuits are provided herein. In an embodiment, a method of forming an integrated circuit includes providing a base substrate having an embedded electrical contact disposed therein. An interlayer dielectric is formed overlying the base substrate, and a recess is etched through the interlayer dielectric over the embedded electrical contact. A protecting liner is formed in the recess and over an exposed surface of the embedded electrical contact in the recess. The protecting liner includes at least two liner layers that have materially different etch rates in different etchants. A portion of the protecting liner is removed over the surface of the embedded electrical contact to again expose the surface of the embedded electrical contact in the recess. An embedded electrical interconnect is formed in the recess. The embedded electrical interconnect overlies the protecting liner on sides of the recess.

Abstract translation: 本文提供集成电路和形成集成电路的方法。 在一个实施例中，形成集成电路的方法包括提供其中布置有嵌入式电触头的基底基板。 在基底基板上形成层间电介质，通过嵌入的电触头上的层间电介质蚀刻凹陷。 保护衬垫形成在凹部中并且在凹部中的嵌入式电触点的暴露表面上。 保护衬垫包括至少两个衬垫层，其在不同的蚀刻剂中具有实质上不同的蚀刻速率。 保护衬垫的一部分在嵌入的电触点的表面上被去除，以再次暴露凹陷中嵌入的电触点的表面。 在凹部中形成嵌入式电气互连。 嵌入式电互连覆盖在凹槽侧面上的保护衬垫。