公开(公告)号：US09892970B2

公开(公告)日：2018-02-13

申请号：US15171314

申请日：2016-06-02

Applicant: GLOBALFOUNDRIES INC.

Inventor： Mukta G. Farooq ,  John A. Fitzsimmons ,  Anthony K. Stamper

IPC: H01L21/768 ,  H01L49/02 ,  H01L23/48 ,  H01L21/3105 ,  H01L21/311 ,  H01L23/498 ,  H01L21/3065

CPC classification number: H01L21/76898 ,  H01L21/3065 ,  H01L21/31051 ,  H01L21/311 ,  H01L23/481 ,  H01L23/498 ,  H01L23/49827 ,  H01L23/49894 ,  H01L28/90 ,  H01L28/92

Abstract: One aspect of the disclosure relates to a method of forming an integrated circuit structure. The method may include: providing a substrate having a front side and a back side, the substrate including: a deep trench (DT) capacitor within the substrate extending toward the back side of substrate, and a through silicon via (TSV) adjacent to the DT capacitor within the substrate extending toward the back side of the substrate, the TSV including a metal substantially surrounded by a liner layer and an insulating layer substantially surrounding the liner layer; etching the back side of the substrate to expose the TSV on the back side of the substrate; and forming a first dielectric layer covering the exposed TSV on the back side of the substrate and extending away from the front side of the substrate.

公开(公告)号：US20170352592A1

公开(公告)日：2017-12-07

申请号：US15171314

申请日：2016-06-02

Applicant: GLOBALFOUNDRIES INC.

Inventor： Mukta G. Farooq ,  John A. Fitzsimmons ,  Anthony K. Stamper

IPC: H01L21/768 ,  H01L23/498 ,  H01L21/3105 ,  H01L21/3065 ,  H01L21/311 ,  H01L49/02 ,  H01L23/48

CPC classification number: H01L21/76898 ,  H01L21/3065 ,  H01L21/31051 ,  H01L21/311 ,  H01L23/481 ,  H01L23/498 ,  H01L23/49827 ,  H01L23/49894 ,  H01L28/90 ,  H01L28/92

Abstract: One aspect of the disclosure relates to a method of forming an integrated circuit structure. The method may include: providing a substrate having a front side and a back side, the substrate including: a deep trench (DT) capacitor within the substrate extending toward the back side of substrate, and a through silicon via (TSV) adjacent to the DT capacitor within the substrate extending toward the back side of the substrate, the TSV including a metal substantially surrounded by a liner layer and an insulating layer substantially surrounding the liner layer; etching the back side of the substrate to expose the TSV on the back side of the substrate; and forming a first dielectric layer covering the exposed TSV on the back side of the substrate and extending away from the front side of the substrate.

公开(公告)号：US20170229362A1

公开(公告)日：2017-08-10

申请号：US15017004

申请日：2016-02-05

Applicant: GLOBALFOUNDRIES INC.

Inventor： John A. Fitzsimmons ,  Michael J. Shapiro ,  Natalia Borjemscaia ,  Vincent McGahay

IPC: H01L23/26 ,  H01L23/535 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/26 ,  H01L23/3142 ,  H01L23/535 ,  H01L23/562 ,  H01L23/564 ,  H01L23/585 ,  H01L2924/3025 ,  H01L2924/3512

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to corrosion resistant chip sidewall connections with crackstop structures with a hermetic seal, and methods of manufacture. The structure includes: a guard ring structure surrounding an active region of an integrated circuit chip; an opening formed in the guard ring structure; and a hermetic seal encapsulating the opening and a portion of the guard ring structure, the hermetic seal being structured to prevent moisture ingress to the active region of the integrated circuit chip through the opening.

公开(公告)号：US20170194265A1

公开(公告)日：2017-07-06

申请号：US14984547

申请日：2015-12-30

Applicant: GLOBALFOUNDRIES INC.

Inventor： Michael J. Shapiro ,  John A. Fitzsimmons ,  Natalia Borjemscaia

IPC: H01L23/00 ,  H01L21/768 ,  H01L23/528

CPC classification number: H01L23/562 ,  H01L21/76879 ,  H01L21/76883 ,  H01L21/76898 ,  H01L22/14 ,  H01L23/528

Abstract: The disclosure generally relates to semiconductor structures and, more particularly, to electrical connections used with crackstop structures and methods of manufacture. The structure includes: a conductive material; a dielectric material formed over the conductive material; a non-corrosive conductive material in at least one opening of the dielectric material and in direct contact with the conductive material; a crackstop structure formed over the dielectric material; and at least one of wiring layer in contact with the non-corrosive conductive material.

公开(公告)号：US20170186643A1

公开(公告)日：2017-06-29

申请号：US14982576

申请日：2015-12-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Anthony K. Stamper ,  Mukta G. Farooq ,  John A. Fitzsimmons ,  Mark D. Jaffe ,  Randy L. Wolf

IPC: H01L21/762 ,  H01L27/13

CPC classification number: H01L21/76256 ,  H01L21/6835 ,  H01L21/7624 ,  H01L27/13 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381

Abstract: Assemblies including a device layer of a silicon-on-insulator (SOI) substrate and a replacement substrate replacing a handle wafer of the SOI substrate, and methods for transferring the device layer of the SOI substrate from the handle wafer to the replacement substrate. A device structure is formed in a first section of the handle wafer, and a second section of the handle wafer adjoining the first section of the handle wafer is removed to expose a surface of the buried dielectric layer of the silicon-on-insulator substrate. A permanent substrate is attached to the surface of the buried dielectric layer. When the permanent substrate is attached to the surface of the buried dielectric layer, the section of the handle wafer is received inside a cavity defined in the permanent substrate.

公开(公告)号：US09257336B2

公开(公告)日：2016-02-09

申请号：US14522633

申请日：2014-10-24

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Mukta G. Farooq ,  John A. Fitzsimmons ,  Troy L. Graves-Abe

IPC: H01L21/44 ,  H01L21/768 ,  H01L21/683 ,  H01L23/00

CPC classification number: H01L21/76898 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/76879 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2221/68359 ,  H01L2224/03462 ,  H01L2224/03622 ,  H01L2224/0401 ,  H01L2224/05556 ,  H01L2224/05572 ,  H01L2224/05611 ,  H01L2224/05639 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05671 ,  H01L2224/11 ,  H01L2224/13025 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/94 ,  Y10T29/41 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2224/03 ,  H01L2924/014

Abstract: According to one embodiment of the present invention, a method of plating a TSV hole in a substrate is provided. The TSV hole may include an open end terminating at a conductive pad, a stack of wiring levels, and a plurality of chip interconnects. The method of plating a TSV may include attaching a handler to the plurality of chip interconnects, the handler having a conductive layer in electrical contact with the plurality of chip interconnects; exposing a closed end of the TSV hole, including the conductive pad, to an electrolyte solution; and applying an electrical potential along an electrical path from the conductive layer to the conductive pad causing conductive material from the electrolyte solution to deposit on the conductive pad and within the TSV hole, the electrical path including the conductive layer, the plurality of chip interconnects, the stack of wiring levels and the conductive pad.

公开(公告)号：US10037911B2

公开(公告)日：2018-07-31

申请号：US15692666

申请日：2017-08-31

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Anthony K. Stamper ,  Mukta G. Farooq ,  John A. Fitzsimmons ,  Mark D. Jaffe ,  Randy L. Wolf

IPC: H01L21/762 ,  H01L27/13

Abstract: Assemblies including a device layer of a silicon-on-insulator (SOI) substrate and a replacement substrate replacing a handle wafer of the SOI substrate, and methods for transferring the device layer of the SOI substrate from the handle wafer to the replacement substrate. A device structure is formed in a first section of the handle wafer, and a second section of the handle wafer adjoining the first section of the handle wafer is removed to expose a surface of the buried dielectric layer of the silicon-on-insulator substrate. A permanent substrate is attached to the surface of the buried dielectric layer. When the permanent substrate is attached to the surface of the buried dielectric layer, the section of the handle wafer is received inside a cavity defined in the permanent substrate.

公开(公告)号：US09929085B2

公开(公告)日：2018-03-27

申请号：US15171320

申请日：2016-06-02

Applicant: GLOBALFOUNDRIES INC.

Inventor： John A. Fitzsimmons ,  Mukta G. Farooq ,  Anthony K. Stamper

IPC: H01L23/522 ,  H01L23/498 ,  H01L21/48 ,  H01L49/02

CPC classification number: H01L23/5223 ,  H01L21/4846 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/76898 ,  H01L23/498 ,  H01L23/49827 ,  H01L23/49894 ,  H01L28/40

Abstract: One aspect of the disclosure relates to an interposer. The interposer may include: a first dielectric layer extending from a substrate in a direction away from a front side of the substrate; a back-end-of-the-line (BEOL) region extending from the substrate in a direction away from the back side of the substrate; a deep trench (DT) capacitor within the substrate and extending toward a back side of the substrate, the DT capacitor having a first portion within the substrate and a second portion within the first dielectric layer; and a through silicon via (TSV) adjacent to the DT capacitor and extending through the first dielectric layer, the substrate, and the BEOL region.

公开(公告)号：US20180005873A1

公开(公告)日：2018-01-04

申请号：US15692666

申请日：2017-08-31

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Anthony K. Stamper ,  Mukta G. Farooq ,  John A. Fitzsimmons ,  Mark D. Jaffe ,  Randy L. Wolf

IPC: H01L21/762 ,  H01L27/13

CPC classification number: H01L21/76256 ,  H01L21/6835 ,  H01L21/7624 ,  H01L27/13 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381

Abstract: Assemblies including a device layer of a silicon-on-insulator (SOI) substrate and a replacement substrate replacing a handle wafer of the SOI substrate, and methods for transferring the device layer of the SOI substrate from the handle wafer to the replacement substrate. A device structure is formed in a first section of the handle wafer, and a second section of the handle wafer adjoining the first section of the handle wafer is removed to expose a surface of the buried dielectric layer of the silicon-on-insulator substrate. A permanent substrate is attached to the surface of the buried dielectric layer. When the permanent substrate is attached to the surface of the buried dielectric layer, the section of the handle wafer is received inside a cavity defined in the permanent substrate.

公开(公告)号：US20170352618A1

公开(公告)日：2017-12-07

申请号：US15171320

申请日：2016-06-02

Applicant: GLOBALFOUNDRIES INC.

Inventor： John A. Fitzsimmons ,  Mukta G. Farooq ,  Anthony K. Stamper

IPC: H01L23/522 ,  H01L23/498 ,  H01L21/48 ,  H01L49/02

CPC classification number: H01L23/5223 ,  H01L21/4846 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/76898 ,  H01L23/498 ,  H01L23/49827 ,  H01L23/49894 ,  H01L28/40

Abstract: One aspect of the disclosure relates to an interposer. The interposer may include: a first dielectric layer extending from a substrate in a direction away from a front side of the substrate; a back-end-of-the-line (BEOL) region extending from the substrate in a direction away from the back side of the substrate; a deep trench (DT) capacitor within the substrate and extending toward a back side of the substrate, the DT capacitor having a first portion within the substrate and a second portion within the first dielectric layer; and a through silicon via (TSV) adjacent to the DT capacitor and extending through the first dielectric layer, the substrate, and the BEOL region.