公开(公告)号：US10083971B1

公开(公告)日：2018-09-25

申请号：US15654190

申请日：2017-07-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Manfred Eller ,  Kwan-Yong Lim

IPC: H01L27/11 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L27/1104 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/785

Abstract: A vertical SRAM cell includes a first (1st) inverter having a 1st common gate structure operatively connecting channels of a 1st pull-up (PU) and a 1st pull-down (PD) transistor. A 1st metal contact electrically connects bottom source/drain (S/D) regions of the 1st PU and 1st PD transistors. A second (2nd) inverter has a 2nd common gate structure operatively connecting channels of a 2nd PU and a 2nd PD transistor. A 2nd metal contact electrically connects bottom S/D regions of the 2nd PU and 2nd PD transistors. A 1st cross-coupled contact electrically connects the 2nd common gate structure to the 1st metal contact. The 2nd common gate structure entirely surrounds a perimeter of the 1st cross-coupled contact. A 2nd cross-coupled contact electrically connects the 1st common gate structure to the 2nd metal contact. The 1st common gate structure entirely surrounds a perimeter of the 2nd cross-coupled contact.

公开(公告)号：US10068978B2

公开(公告)日：2018-09-04

申请号：US15472924

申请日：2017-03-29

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kwan-Yong Lim ,  Christopher Michael Prindle

IPC: H01L29/06 ,  H01L29/417 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/66 ,  G06F17/50 ,  H01L29/45 ,  H01L29/78 ,  H01L29/165

Abstract: At least one method, apparatus and system disclosed herein for suppressing over-growth of epitaxial layer formed on fins of fin field effect transistor (finFET) to prevent shorts between fins of separate finFET devices. A set of fins of a first transistor is formed. The set of fins comprises a first outer fin, an inner fin, and a second outer fin. An oxide deposition process is performed for depositing an oxide material upon the set of fins. A first recess process is performed for removing a portion of oxide material. This leaves a portion of the oxide material remaining on the inside walls of the first and second outer fins. A spacer nitride deposition process is performed. A spacer nitride removal process is performed, leaving spacer nitride material at the outer walls of the first and second outer fins. A second recess process is performed for removing the oxide material from the inside walls of the first and second outer fins. An epitaxial layer deposition processed upon the set of fins. A portion of the lateral over-growth of epitaxial layer on the outer walls of the first and second outer fins is suppressed by the spacer nitride material.

公开(公告)号：US09929236B1

公开(公告)日：2018-03-27

申请号：US15624762

申请日：2017-06-16

Applicant: GLOBALFOUNDRIES INC.

Inventor： Bipul C. Paul ,  Kwan-Yong Lim

IPC: H01L29/786 ,  H01L29/06 ,  H01L27/11 ,  H01L29/423 ,  H01L21/8238

CPC classification number: H01L27/1108 ,  H01L21/823814 ,  H01L21/823885

Abstract: Methods form structures to include a first pair of complementary transistors (having first and second transistors) and a second pair of complementary transistors (having third and fourth transistors). An active area of the first transistor contacts an active area of the second transistor along a first common edge that is straight, and an active area of the third transistor contacts an active area of the fourth transistor along a second common edge that is straight and parallel to the first common edge. The active area of the second transistor has a third edge, opposite the first common edge, that has a non-linear shape, and the active area of the third transistor has a fourth edge, opposite the second common edge, that has the same non-linear shape. The non-linear shape of the third edge faces and is inverted relative to the non-linear shape of the fourth edge.

公开(公告)号：US09837404B2

公开(公告)日：2017-12-05

申请号：US15082242

申请日：2016-03-28

Applicant: GLOBALFOUNDRIES INC.

Inventor： Min Gyu Sung ,  Chanro Park ,  Hoon Kim ,  Ruilong Xie ,  Kwan-Yong Lim

IPC: H01L21/336 ,  H01L29/66 ,  H01L29/78 ,  H01L21/308 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/3105 ,  H01L21/311

CPC classification number: H01L27/0886 ,  H01L21/31053 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/823821 ,  H01L21/845 ,  H01L29/66795 ,  H01L29/785

Abstract: At least one method, apparatus and system are disclosed for forming a fin field effect transistor (finFET) having an oxide level in a fin array region within a predetermined height of the oxide level of a field region. A first oxide process is performed for controlling a first oxide recess level in a field region adjacent to a fin array region comprising a plurality of fins in a finFET device. The first oxide process comprises depositing an oxide layer over the field region and the fin array region and performing an oxide recess process to bring the oxide layer to the first oxide recess level in the field region. A second oxide process is performed for controlling a second oxide recess level in the fin array region. The second oxide process comprises isolating the fin array region, depositing oxide material, and performing an oxide recess process to bring the oxide level in the fin array region to the second oxide recess level. The first oxide recess level is within a predetermined height differential of the second oxide recess level.

公开(公告)号：US20170141211A1

公开(公告)日：2017-05-18

申请号：US15168690

申请日：2016-05-31

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Kwan-Yong Lim ,  Min Gyu Sung ,  Ryan Ryoung-Han Kim

IPC: H01L29/66 ,  H01L27/088 ,  H01L29/06

CPC classification number: H01L29/66545 ,  H01L21/76224 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7851

Abstract: One illustrative integrated circuit product disclosed herein includes, among other things, a plurality of FinFET devices, each of which comprises a gate structure comprising a high-k gate insulation material and at least one layer of metal, a single diffusion break (SDB) isolation structure positioned in a first trench defined in a semiconductor substrate between first and second active regions, the SDB isolation structure comprising the high-k insulating material and the at least one layer of metal, and a double diffusion break (DDB) isolation structure positioned in a second trench defined in a semiconductor substrate between third and fourth active regions, the DDB isolation structure comprising a first insulating material that substantially fills the second trench.

公开(公告)号：US09640636B1

公开(公告)日：2017-05-02

申请号：US15171795

申请日：2016-06-02

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Steven J. Bentley ,  John H. Zhang ,  Kwan-Yong Lim ,  Hiroaki Niimi

IPC: H01L21/8234 ,  H01L29/66 ,  H01L29/06 ,  H01L29/417 ,  H01L29/08 ,  H01L21/306 ,  H01L21/02

CPC classification number: H01L29/66666 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823487 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/41741 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/7827

Abstract: One illustrative method disclosed herein includes, among other things, forming an initial vertically oriented channel semiconductor structure having a first height above a substrate, forming a sacrificial spacer structure adjacent the initial vertically oriented channel semiconductor structure and, with the sacrificial spacer in position, performing at least one process operation to define a self-aligned bottom source/drain region for the device that is self-aligned with respect to the sacrificial spacer structure, forming an isolation region in the trench and forming a bottom source/drain electrode above the isolation region. The method also includes removing the sacrificial spacer structure and forming a bottom spacer material around the vertically oriented channel semiconductor structure above the bottom source/drain electrode.

公开(公告)号：US09530866B1

公开(公告)日：2016-12-27

申请号：US15097621

申请日：2016-04-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： John H. Zhang ,  Carl Radens ,  Steven J. Bentley ,  Brian A. Cohen ,  Kwan-Yong Lim

IPC: H01L21/02 ,  H01L21/265 ,  H01L21/3105 ,  H01L29/66

CPC classification number: H01L29/66666 ,  B82Y10/00 ,  H01L29/0676 ,  H01L29/401 ,  H01L29/41741 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/7827

Abstract: Forming a first sidewall spacer adjacent a vertically oriented channel semiconductor structure (“VCS structure’) and adjacent a cap layer, performing at least one planarization process so as to planarize an insulating material and expose an upper surface of the cap layer and an upper surface of the first spacer and removing a portion of the first spacer and an entirety of the cap layer so as to thereby expose an upper surface of the VCS structure and define a spacer/contact cavity above the VCS structure and the first spacer. The method also includes forming a second spacer in the spacer/contact cavity, forming a top source/drain region in the VCS structure and forming a top source/drain contact within the spacer/contact cavity that is conductively coupled to the top source/drain region, wherein the conductive contact physically contacts the second spacer in the spacer/contact cavity.

Abstract translation: 形成与垂直取向的沟道半导体结构（“VCS结构”）相邻并且与覆盖层相邻的第一侧壁间隔物，执行至少一个平坦化处理，以平坦化绝缘材料并暴露盖层的上表面和上表面 并且去除所述第一间隔物的一部分和所述盖层的整体，从而暴露所述VCS结构的上表面并且在所述VCS结构和所述第一间隔物之上限定间隔物/接触腔。 该方法还包括在间隔物/接触腔中形成第二间隔物，在VCS结构中形成顶部源极/漏极区域，并在间隔物/接触腔内形成顶部源极/漏极接触，导电耦合到顶部源极/漏极 区域，其中所述导电接触物质地接触所述间隔件/接触腔中的所述第二间隔件。

公开(公告)号：US09362279B1

公开(公告)日：2016-06-07

申请号：US14609171

申请日：2015-01-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Andy Wei ,  William James Taylor ,  Ryan Ryoung-han Kim ,  Kwan-Yong Lim ,  Chanro Park

IPC: H01L27/088 ,  H01L29/66 ,  H01L21/762 ,  H01L21/02 ,  H01L21/8234 ,  H01L29/417

CPC classification number: H01L27/0886 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/02282 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/28518 ,  H01L21/76224 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823475 ,  H01L21/823481 ,  H01L29/165 ,  H01L29/41775 ,  H01L29/41791 ,  H01L29/66545

Abstract: A method of contact formation and resulting structure is disclosed. The method includes providing a starting semiconductor structure, the structure including a semiconductor substrate with fins coupled to the substrate, a bottom portion of the fins being surrounded by a first dielectric layer, dummy gates covering a portion of each of the fins, spacers and a cap for each dummy gate, and a lined trench between the gates extending to and exposing the first dielectric layer. The method further includes creating an epitaxy barrier of hard mask material between adjacent fins in the trench, creating N and P type epitaxial material on the fins adjacent opposite sides of the barrier, and creating sacrificial semiconductor epitaxy over the N and P type epitaxial material, such that subsequent removal thereof can be done selective to the N and P type of epitaxial material. The resulting structure has replacement (conductive) gates, conductive material above the N and P type epitaxy, and a contact to the conductive material for each of N and P type epitaxy.

Abstract translation: 公开了接触形成方法和结构。 该方法包括提供起始半导体结构，该结构包括具有耦合到基板的翅片的半导体基板，翅片的底部被第一介电层包围，覆盖每个翅片的一部分的虚拟栅极，间隔件和 每个虚拟栅极的盖，以及延伸到第一介电层并暴露第一介电层的栅极之间的衬里沟槽。 该方法还包括在沟槽中的相邻散热片之间产生硬掩模材料的外延屏障，在邻近屏障相对侧的鳍片上产生N和P型外延材料，并在N和P型外延材料上产生牺牲半导体外延， 使得随后的去除可以对N型和P型外延材料选择性地进行。 所得结构具有替代（导电）栅极，N和P型外延上方的导电材料，以及N和P型外延中的每一个与导电材料的接触。

公开(公告)号：US09236452B2

公开(公告)日：2016-01-12

申请号：US14286400

申请日：2014-05-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Kwan-Yong Lim ,  Jody Fronheiser ,  Christopher Prindle

IPC: H01L29/66 ,  H01L29/08

CPC classification number: H01L29/0847 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785

Abstract: A method of forming raised S/D regions by partial EPI growth with a partial EPI liner therebetween and the resulting device are provided. Embodiments include forming groups of fins extending above a STI layer; forming a gate over the groups of fins; forming a gate spacer on each side of the gate; forming a raised S/D region proximate to each spacer on each fin of the groups of fins, each raised S/D region having a top surface, vertical sidewalls, and an undersurface; forming a liner over and between each raised S/D region; removing the liner from the top surface of each raised S/D region and from in between a group of fins; forming an overgrowth region on the top surface of each raised S/D region; forming an ILD over and between the raised S/D regions; and forming a contact through the ILD, down to the raised S/D regions.

Abstract translation: 提供通过部分EPI生长形成凸起S / D区域的方法，其中部分EPI衬垫在其间，并且提供所得到的装置。 实施例包括形成在STI层上延伸的翅片组; 在翅片组上形成一个门; 在栅极的每一侧上形成栅极间隔物; 在所述翅片组的每个翅片上形成靠近每个间隔件的凸起S / D区域，每个凸起的S / D区域具有顶表面，垂直侧壁和下表面; 在每个凸起的S / D区域之间和之间形成衬垫; 从每个凸起的S / D区域的顶表面和一组翅片之间移除衬垫; 在每个凸起的S / D区域的上表面上形成过度生长区域; 在升高的S / D区域之间形成ILD; 并通过ILD形成接触，直到升高的S / D区域。

公开(公告)号：US10580779B2

公开(公告)日：2020-03-03

申请号：US15903203

申请日：2018-02-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Kwan-Yong Lim ,  Ryan Ryoung-Han Kim

IPC: H01L27/11 ,  G11C8/14 ,  H01L23/522 ,  H01L21/768 ,  H01L27/105 ,  H01L21/48 ,  H01L23/50

Abstract: A memory cell includes vertical transistors including first and second pass gate (PG) transistors, first and second pull-up (PU1 and PU2) transistors, and first and second pull-down (PD1 and PD2) transistors. A first bottom electrode connects bottom source/drain (SD) regions of PU1 and PU2. A second bottom electrode connects bottom SD regions of PD1 and PD2. A first shared contact connects the top SD region of PU2 to the gate structure of PU1. A second shared contact connects the top SD region of PD1 to the gate structure of PD2. A first top electrode is connected to the top SD regions of PG1, PU1 and the second shared contact to define a first storage node of the memory cell. A second top electrode is connected to the top SD regions of PG2, PU2 and the first shared contact to define a second storage node of the memory cell.