公开(公告)号：US20160315162A1

公开(公告)日：2016-10-27

申请号：US15201838

申请日：2016-07-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ralf Richter ,  Peter Javorka ,  Jan Hoentschel ,  Stefan Flachowsky

IPC: H01L29/423 ,  H01L21/28 ,  H01L29/51 ,  H01L29/49

CPC classification number: H01L29/42376 ,  H01L21/28008 ,  H01L21/28052 ,  H01L21/28114 ,  H01L21/28123 ,  H01L29/4933 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66575 ,  H01L29/78

Abstract: A semiconductor device structure includes an active region positioned in a semiconductor substrate and a gate structure of a transistor positioned above the active region. The gate structure includes a gate insulating layer, a gate metal layer positioned above the gate insulating layer and a trimmed gate electrode material layer positioned above the gate metal layer. A length of at least a portion of the trimmed gate electrode material layer in a gate length direction of the transistor is less than a length of at least the gate metal layer in the gate length direction.

Abstract translation: 半导体器件结构包括位于半导体衬底中的有源区和位于有源区上方的晶体管的栅极结构。 栅极结构包括栅极绝缘层，位于栅极绝缘层上方的栅极金属层和位于栅极金属层上方的修整的栅电极材料层。 在晶体管的栅极长度方向上的修整的栅电极材料层的至少一部分的长度小于栅极金属层在栅极长度方向上的长度。

公开(公告)号：US20160233318A1

公开(公告)日：2016-08-11

申请号：US14615529

申请日：2015-02-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ralf Richter ,  Peter Javorka ,  Jan Hoentschel ,  Stefan Flachowsky

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/42392 ,  H01L29/66772 ,  H01L29/78696

Abstract: The present disclosure provides a method of forming a semiconductor device and a semiconductor device. An SOI substrate portion having a semiconductor layer, a buried insulating material layer and a bulk substrate is provided, wherein the buried insulating material layer is interposed between the semiconductor layer and the bulk substrate. The SOI substrate portion is subsequently patterned so as to form a patterned bi-layer stack on the bulk substrate, which bi-layer stack comprises a patterned semiconductor layer and a patterned buried insulating material layer. The bi-layer stack is further enclosed with a further insulating material layer and an electrode material is formed on and around the further insulating material layer. Herein a gate electrode is formed by the bulk substrate and the electrode material such that the gate electrode substantially surrounds a channel portion formed by a portion of the patterned buried insulating material layer.

Abstract translation: 本公开提供了形成半导体器件和半导体器件的方法。 提供具有半导体层，掩埋绝缘材料层和体基板的SOI衬底部分，其中埋入绝缘材料层插入在半导体层和块状衬底之间。 SOI衬底部分随后被图案化以便在本体衬底上形成图案化的双层堆叠，该双层堆叠包括图案化的半导体层和图案化的掩埋绝缘材料层。 双层堆叠进一步被另外的绝缘材料层封闭，并且在另外的绝缘材料层上和周围形成电极材料。 这里，栅电极由体基板和电极材料形成，使得栅电极基本上围绕由图案化的掩埋绝缘材料层的一部分形成的沟道部分。

公开(公告)号：US09412859B2

公开(公告)日：2016-08-09

申请号：US13792730

申请日：2013-03-11

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ralf Richter ,  Peter Javorka ,  Jan Hoentschel ,  Stefan Flachowsky

IPC: H01L29/78 ,  H01L21/28 ,  H01L29/66 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51

CPC classification number: H01L29/42376 ,  H01L21/28008 ,  H01L21/28052 ,  H01L21/28114 ,  H01L21/28123 ,  H01L29/4933 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66575 ,  H01L29/78

Abstract: Methods for forming a semiconductor device are provided. In one embodiment, a gate structure having a gate insulating layer and a gate electrode structure formed on the gate insulating layer is provided. The methods provide reducing a dimension of the gate electrode structure relative to the gate insulating layer along a direction extending in parallel to a direction connecting the source and drain. A semiconductor device structure having a gate structure including a gate insulating layer and a gate electrode structure formed above the gate insulating layer is provided, wherein a dimension of the gate electrode structure extending along a direction which is substantially parallel to a direction being oriented from source to drain is reduced relative to a dimension of the gate insulating layer. According to some examples, gate structures are provided having a gate silicon length which is decoupled from the channel width induced by the gate structure.

Abstract translation: 提供了形成半导体器件的方法。 在一个实施例中，提供了一种在栅极绝缘层上形成栅极绝缘层和栅电极结构的栅极结构。 所述方法提供了沿着平行于连接源极和漏极的方向延伸的方向，相对于栅极绝缘层减小栅电极结构的尺寸。 提供一种具有栅极结构的半导体器件结构，该栅极结构包括形成在栅极绝缘层上方的栅极绝缘层和栅电极结构，其中栅电极结构的尺寸沿着基本上平行于源极方向的方向延伸 漏极相对于栅极绝缘层的尺寸减小。 根据一些示例，提供具有栅极硅长度的栅极结构，其与由栅极结构引起的沟道宽度解耦。

公开(公告)号：US09373720B2

公开(公告)日：2016-06-21

申请号：US14052977

申请日：2013-10-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Stefan Flachowsky ,  Jan Hoentschel ,  Ralf Richter ,  Peter Javorka

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/7843 ,  H01L21/823412 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/161 ,  H01L29/66795 ,  H01L29/785

Abstract: The present invention relates to a semiconductor structure comprising at least a first and a second three-dimensional transistor, wherein the first transistor and the second transistor are electrically connected in parallel to each other, and wherein each transistor comprises a source and a drain, wherein the source and/or drain of the first transistor is at least partially separated from, respectively, the source and/or drain of the second transistor. The invention further relates to a process for realizing such a semiconductor structure.

Abstract translation: 本发明涉及包括至少第一和第二三维晶体管的半导体结构，其中第一晶体管和第二晶体管彼此并联电连接，并且其中每个晶体管包括源极和漏极，其中 第一晶体管的源极和/或漏极分别与第二晶体管的源极和/或漏极部分地分开。 本发明还涉及一种用于实现这种半导体结构的方法。

公开(公告)号：US09373509B2

公开(公告)日：2016-06-21

申请号：US14477358

申请日：2014-09-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ralf Richter ,  Stefan Flachowsky ,  Peter Javorka ,  Jan Hoentschel

IPC: H01L21/30 ,  C23C14/48 ,  H01L21/336 ,  H01L21/265 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/266 ,  H01L21/3065 ,  H01J37/32

CPC classification number: H01L21/26586 ,  H01J37/32412 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/3065 ,  H01L21/823431 ,  H01L29/66803 ,  H01L29/7851

Abstract: A method to implant dopants onto fin-type field-effect-transistor (FINFET) fin surfaces with uniform concentration and depth levels of the dopants and the resulting device are disclosed. Embodiments include a method for pulsing a dopant perpendicular to an upper surface of a substrate, forming an implantation beam pulse; applying an electric or a magnetic field to the implantation beam pulse to effectuate a curvilinear trajectory path of the implantation beam pulse; and implanting the dopant onto a sidewall surface of a target FINFET fin on the upper surface of the substrate via the curvilinear trajectory path of the implantation beam pulse.

Abstract translation: 公开了将掺杂剂注入到具有均匀的掺杂剂和所得器件的浓度和深度水平的鳍式场效应晶体管（FINFET）鳍表面上的方法。 实施例包括用于脉冲掺杂物垂直于衬底的上表面的方法，形成注入束脉冲; 对注入束脉冲施加电场或磁场，以实现注入束脉冲的曲线轨迹路径; 以及通过所述注入束脉冲的曲线轨迹路径将所述掺杂剂注入到所述衬底的上表面上的靶FINFET鳍的侧壁表面上。

公开(公告)号：US20160163815A1

公开(公告)日：2016-06-09

申请号：US14693978

申请日：2015-04-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jan Hoentschel ,  Stefan Flachowsky ,  Ralf Richter ,  Peter Javorka

IPC: H01L29/66 ,  H01L29/45 ,  H01L29/06 ,  H01L21/283 ,  H01L29/78

CPC classification number: H01L29/665 ,  H01L21/283 ,  H01L21/28518 ,  H01L21/76897 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/0629 ,  H01L27/092 ,  H01L29/0653 ,  H01L29/45 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/7834 ,  H01L29/7843 ,  H01L29/7848

Abstract: The present disclosure provides in one aspect for a semiconductor device structure which may be formed by providing source/drain regions within a semiconductor substrate in alignment with a gate structure formed over the semiconductor substrate, wherein the gate structure has a gate electrode structure, a first sidewall spacer and a second sidewall spacer, the first sidewall spacer covering sidewall surfaces of the gate electrode structure and the sidewall spacer being formed on the first sidewall spacer. Furthermore, forming the semiconductor device structure may include removing the second sidewall spacer so as to expose the first sidewall spacer, forming a third sidewall spacer on a portion of the first sidewall spacer such that the first sidewall spacer is partially exposed, and forming silicide regions in alignment with the third sidewall spacer in the source/drain regions.

Abstract translation: 本公开在一个方面中提供了半导体器件结构，其可以通过在半导体衬底内提供与在半导体衬底上形成的栅极结构对准的源极/漏极区域形成，其中栅极结构具有栅电极结构，第一 侧壁间隔件和第二侧壁间隔件，所述第一侧壁间隔物覆盖所述栅极电极结构和所述侧壁间隔物的侧壁表面，所述侧壁间隔件形成在所述第一侧壁间隔物上。 此外，形成半导体器件结构可以包括去除第二侧壁间隔物以暴露第一侧壁间隔物，在第一侧壁间隔物的一部分上形成第三侧壁间隔物，使得第一侧壁间隔物部分地暴露，并且形成硅化物区域 与源极/漏极区域中的第三侧壁间隔物对准。

公开(公告)号：US09349734B2

公开(公告)日：2016-05-24

申请号：US14475720

申请日：2014-09-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Peter Javorka ,  Stefan Flachowsky ,  Gerd Zschätzsch

IPC: H01L21/336 ,  H01L27/092 ,  H01L29/78 ,  H01L29/49 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/02 ,  H01L21/308 ,  H01L21/311 ,  H01L27/06

CPC classification number: H01L27/0922 ,  H01L21/02532 ,  H01L21/28097 ,  H01L21/3083 ,  H01L21/8238 ,  H01L21/823814 ,  H01L21/823835 ,  H01L21/823842 ,  H01L27/0629 ,  H01L27/092 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/24 ,  H01L29/267 ,  H01L29/4941 ,  H01L29/4975 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/7848

Abstract: The present disclosure provides a method of forming a semiconductor device structure with selectively fabricating semiconductor device structures having fully silicided (FuSi) gates and partially silicided gates. In aspects of the present disclosure, a semiconductor device structure with a first semiconductor device and a second semiconductor device is provided, wherein each of the first and second semiconductor devices includes a gate structure over an active region, each of the gate structures having a gate electrode material and a gate dielectric material. The gate electrode material of the first semiconductor device is recessed, resulting in a recessed first gate electrode material which is fully silicided during a subsequent silicidation process. On the gate electrode material of the second semiconductor device, a silicide portion is formed during the silicidation process.

Abstract translation: 本公开提供了一种形成半导体器件结构的方法，其选择性地制造具有完全硅化（FuSi）栅极和部分硅化栅极的半导体器件结构。 在本公开的方面中，提供了具有第一半导体器件和第二半导体器件的半导体器件结构，其中第一和第二半导体器件中的每一个在有源区域上包括栅极结构，每个栅极结构具有栅极 电极材料和栅极电介质材料。 第一半导体器件的栅电极材料凹陷，导致凹陷的第一栅电极材料，其在随后的硅化工艺期间被完全硅化。 在第二半导体器件的栅极电极材料上，在硅化处理期间形成硅化物部分。

公开(公告)号：US20160071978A1

公开(公告)日：2016-03-10

申请号：US14944833

申请日：2015-11-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Peter Javorka ,  Stephan Kronholz ,  Gunda Beernink

IPC: H01L29/78 ,  H01L29/04 ,  H01L29/165 ,  H01L29/10

CPC classification number: H01L29/7848 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823425 ,  H01L29/04 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/41783 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7834

Abstract: A semiconductor device includes drain and source regions positioned in an active region of a transistor and a channel region positioned laterally between the drain and source regions that includes a semiconductor base material and a threshold voltage adjusting semiconductor material positioned on the semiconductor base material. A gate electrode structure is positioned on the threshold voltage adjusting semiconductor material, and a strain-inducing semiconductor alloy including a first semiconductor material and a second semiconductor material positioned above the first semiconductor material is embedded in the semiconductor base material of the active region. A crystalline buffer layer of a third semiconductor material surrounds the embedded strain-inducing semiconductor alloy, wherein an upper portion of the crystalline buffer layer laterally confines the channel region including the sidewalls of the threshold voltage adjusting semiconductor material and is positioned between the second semiconductor material and the threshold voltage adjusting semiconductor material.

Abstract translation: 半导体器件包括位于晶体管的有源区域中的漏极和源极区域以及横向设置在漏极和源极区域之间的沟道区域，该沟道区域包括位于半导体基底材料上的半导体基底材料和阈值电压调节半导体材料。 门极电极结构位于阈值电压调节用半导体材料上，并且包含位于第一半导体材料上方的第一半导体材料和第二半导体材料的应变诱发半导体合金嵌入有源区的半导体基底材料中。 第三半导体材料的结晶缓冲层包围嵌入式应变诱导半导体合金，其中结晶缓冲层的上部横向限制包括阈值电压调节半导体材料的侧壁的沟道区，并且位于第二半导体材料 和阈值电压调节半导体材料。

公开(公告)号：US09093526B2

公开(公告)日：2015-07-28

申请号：US13713085

申请日：2012-12-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Peter Javorka ,  Juergen Faul ,  Bastian Haussdoerfer

IPC: H01L21/311 ,  H01L29/78 ,  H01L21/314 ,  H01L29/66

CPC classification number: H01L29/7833 ,  H01L21/31116 ,  H01L21/314 ,  H01L29/66598 ,  H01L29/78

Abstract: A method of forming a spacer is disclosed that involves forming a layer of spacer material above an etch stop layer, performing a first main etching process on the layer of spacer material to remove some of material, stopping the etching process prior to exposing the etch stop layer and performing a second over-etch process on the layer of spacer material, using the following parameters: an inert gas flow rate of about 50-200 sscm, a reactive gas flow rate of about 3-20 sscm, a passivating gas flow rate of about 3-20 sscm, a processing pressure about 5-15 mT, a power level of about 200-500 W for ion generation and a bias voltage of about 300-500 V. A device includes a gate structure positioned above a semiconducting substrate, a substantially triangular-shaped sidewall spacer positioned proximate the gate structure and an etch stop layer positioned between the spacer and the gate structure.

Abstract translation: 公开了一种形成间隔物的方法，其包括在蚀刻停止层上方形成间隔物材料层，在间隔物材料层上进行第一主蚀刻工艺以去除一些材料，在暴露蚀刻停止点之前停止蚀刻工艺 层，并且使用以下参数对间隔材料层进行第二过蚀刻工艺：约50-200scscm的惰性气体流速，约3-20scscm的反应气体流速，钝化气体流速 约3-20sccm的加工压力，约5-15mT的加工压力，用于离子产生的约200-500W的功率水平和约300-500V的偏置电压。一种器件包括位于半导体衬底上方的栅极结构 位于栅极结构附近的基本为三角形的侧壁间隔件，以及位于间隔件和栅极结构之间的蚀刻停止层。

公开(公告)号：US20140264632A1

公开(公告)日：2014-09-18

申请号：US14167001

申请日：2014-01-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ralf Richter ,  Jan Hoentschel ,  Peter Javorka

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/66795 ,  H01L29/41791 ,  H01L29/7833 ,  H01L29/7845 ,  H01L29/785

Abstract: A semiconductor structure is provided including a transistor, the transistor including one or more elongated semiconductor regions, each of the one or more elongated semiconductor regions having a channel region, a gate electrode, wherein the gate electrode is provided at least at two opposite sides of each of the one or more elongated semiconductor regions, and a layer of a stress-creating material, the stress-creating material providing a variable stress, wherein the layer of stress-creating material is arranged to provide a stress at least in the channel region of each of the one or more elongated semiconductor regions, the stress provided in the channel region of each of the one or more elongated semiconductor regions being variable.

Abstract translation: 提供了包括晶体管的半导体结构，所述晶体管包括一个或多个细长半导体区域，所述一个或多个细长半导体区域中的每一个具有沟道区域，栅极电极，其中所述栅电极至少设置在 所述一个或多个细长半导体区域中的每一个以及应力产生材料层，所述应力产生材料提供可变应力，其中所述应力产生材料层被布置成至少在所述沟道区域中提供应力 所述一个或多个细长半导体区域中的每个的沟道区域中提供的应力是可变的。