公开(公告)号：US10249616B2

公开(公告)日：2019-04-02

申请号：US15627835

申请日：2017-06-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Manfred Eller ,  Haiting Wang ,  Daniel Jaeger

IPC: H01L49/02 ,  H01L21/3213 ,  H01L21/8234 ,  H01L27/06 ,  H01L27/02 ,  H01L29/66 ,  H01L29/78 ,  H01L29/49

Abstract: One illustrative method disclosed herein includes, among other things, forming first and second adjacent gates above a semiconductor substrate, each of the gates comprising a gate structure and a gate cap, forming a conductive resistor structure between the first and second adjacent gates, the conductive resistor structure having an uppermost surface that is positioned at a level that is below a level of an uppermost surface of the gate caps of the first and second adjacent gates, and forming first and second separate conductive resistor contact structures, each of which is conductively coupled to the conductive resistor structure.

公开(公告)号：US20190097015A1

公开(公告)日：2019-03-28

申请号：US15716287

申请日：2017-09-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui Zang ,  Daniel Jaeger ,  Haigou Huang ,  Veeraraghavan Basker ,  Christopher Nassar ,  Jinsheng Gao ,  Michael Aquilino

IPC: H01L29/49 ,  H01L29/66 ,  H01L29/78 ,  H01L21/02 ,  H01L21/225 ,  H01L21/28 ,  H01L21/8234 ,  H01L21/321

CPC classification number: H01L29/4933 ,  H01L21/02425 ,  H01L21/2257 ,  H01L21/28052 ,  H01L21/3212 ,  H01L21/823431 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785

Abstract: At least one method, apparatus and system disclosed herein involves forming trench in a gate region, wherein the trench having an oxide layer to a height to reduce or prevent process residue. A plurality of fins are formed on a semiconductor substrate. Over a first portion of the fins, an epitaxial (EPI) feature at a top portion of each fin of the first portion. Over a second portion of the fins, a gate region is formed. In a portion of the gate region, a trench is formed. A first oxide layer at a bottom region of the trench is formed. Prior to performing an amorphous-silicon (a-Si) deposition, a flowable oxide material is deposited into the trench for forming a second oxide layer. The second oxide layer comprises the flowable oxide and the first oxide layer. The second oxide layer has a first height.

公开(公告)号：US10062612B2

公开(公告)日：2018-08-28

申请号：US15288503

申请日：2016-10-07

Applicant: GLOBALFOUNDRIES INC.

Inventor： David Paul Brunco ,  Daniel Jaeger

IPC: H01L21/8234 ,  H01L27/088 ,  H01L21/02

CPC classification number: H01L21/823431 ,  H01L21/02129 ,  H01L21/823481 ,  H01L21/823821 ,  H01L27/0886 ,  H01L29/66803

Abstract: Generally, the present disclosure is directed to a method for forming a FinFET device that may be used in designs that include both tight and relaxed fin pitches. The method for forming the fins includes: forming a first layer of doped silicate glass above a semiconductor wafer and within a plurality of recesses located adjacent the fins; forming a first layer of nitride above the first doped silicate glass layer; and forming a conformal oxide layer above the first nitride layer, substantially filling relatively narrow recesses between fins having a tight pitch and lining relatively wide recesses between fins having a relaxed pitch.

公开(公告)号：US09780002B1

公开(公告)日：2017-10-03

申请号：US15173766

申请日：2016-06-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xintuo Dai ,  Brian Greene ,  Mahender Kumar ,  Daniel J. Dechene ,  Daniel Jaeger

IPC: H01L21/8238 ,  H01L21/308 ,  H01L21/02 ,  H01L21/027 ,  H01L21/265 ,  H01L21/3115 ,  H01L21/3065 ,  H01L21/762 ,  H01L29/66 ,  H01L27/092 ,  H01L27/02

CPC classification number: H01L21/26506 ,  H01L21/02118 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/0271 ,  H01L21/0276 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/3065 ,  H01L21/3083 ,  H01L21/31155 ,  H01L21/76213 ,  H01L21/76224 ,  H01L21/823814 ,  H01L21/823821 ,  H01L27/0207 ,  H01L27/0924 ,  H01L29/66795 ,  H01L29/66803

Abstract: Methodologies for patterning and implantation are provided Embodiments include forming fins; forming an SiN over the fins; forming an a-Si layer over the SiN; forming and patterning a first patterning layer over the a-Si layer; etching through the a-Si layer using the first patterning layer as a mask; removing the first patterning layer; implanting ions in exposed groups of fins; forming and patterning a second patterning layer to expose a first group of fins and a portion of the a-Si layer on opposite sides of the first group of fins; implanting ions in a first region of the first group of fins; forming a third patterning layer over the first region of the first group of fins and exposing a second region of the first group of fins; and implanting ions in the second region of the first group of fins.

公开(公告)号：US09589829B1

公开(公告)日：2017-03-07

申请号：US14982872

申请日：2015-12-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Huy M. Cao ,  Daniel Jaeger ,  Guillaume Bouche

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/78 ,  H01L21/762 ,  H01L29/06

CPC classification number: H01L21/76224 ,  H01L21/0217 ,  H01L29/0649 ,  H01L29/66795 ,  H01L29/785

Abstract: A method includes forming a plurality of fins on a semiconductor substrate by defining a plurality of trenches in the substrate. A first insulating material layer comprising silicon, oxygen and carbon is formed in the trenches between the plurality of fins. The first insulating material layer has an upper surface that is at a level that is below an upper surface of the fins. A second insulating material layer is formed above the first insulating material layer. The second insulating material layer is planarized to expose a top surface of the plurality of fins. The second insulating material layer is removed to expose the first insulating material layer.

Abstract translation: 一种方法包括通过在衬底中限定多个沟槽，在半导体衬底上形成多个翅片。 在多个翅片之间的沟槽中形成包括硅，氧和碳的第一绝缘材料层。 第一绝缘材料层的上表面位于翅片上表面的下方。 第二绝缘材料层形成在第一绝缘材料层的上方。 第二绝缘材料层被平坦化以暴露多个翅片的顶表面。 去除第二绝缘材料层以露出第一绝缘材料层。

公开(公告)号：US20200335591A1

公开(公告)日：2020-10-22

申请号：US16386363

申请日：2019-04-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Michael Aquilino ,  Daniel Jaeger ,  Naved Siddiqui ,  Jessica Dechene ,  Daniel J. Dechene ,  Shreesh Narasimha ,  Natalia Borjemscaia

IPC: H01L29/417 ,  H01L27/088 ,  H01L21/311 ,  H01L21/033 ,  H01L29/40

Abstract: Structures for a field-effect transistor and methods of forming a field-effect transistor. A sidewall spacer is arranged adjacent to a sidewall of a gate electrode, a source/drain region is arranged laterally adjacent to the sidewall spacer, and a contact is arranged over the source/drain region and laterally adjacent to the sidewall spacer. The contact is coupled with the source/drain region. A section of an interlayer dielectric layer is laterally arranged between the contact and the sidewall spacer.

公开(公告)号：US10460986B2

公开(公告)日：2019-10-29

申请号：US15882291

申请日：2018-01-29

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jinsheng Gao ,  Daniel Jaeger ,  Chih-Chiang Chang ,  Michael Aquilino ,  Patrick Carpenter ,  Junsic Hong ,  Mitchell Rutkowski ,  Haigou Huang ,  Huy Cao

IPC: H01L29/66 ,  H01L21/768 ,  H01L21/28 ,  H01L21/311 ,  H01L29/417

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a cap structure and methods of manufacture. The structure includes: a gate structure composed of conductive gate material; sidewall spacers on the gate structure, extending above the conductive gate material; and a capping material on the conductive gate material and extending over the sidewall spacers on the gate structure.

公开(公告)号：US10325819B1

公开(公告)日：2019-06-18

申请号：US15920303

申请日：2018-03-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jinsheng Gao ,  Daniel Jaeger ,  Michael Aquilino ,  Patrick Carpenter ,  Jessica Dechene ,  Huy Cao ,  Mitchell Rutkowski ,  Haigou Huang

IPC: H01L21/336 ,  H01L21/8238 ,  H01L21/762 ,  H01L21/768 ,  H01L21/306 ,  H01L29/66 ,  H01L21/311 ,  H01L21/3065 ,  H01L21/3105

Abstract: At least one method, apparatus and system disclosed herein involves forming trench silicide region contact. A plurality of fins are formed on a semiconductor substrate. An epitaxial (EPI) feature is formed at a top portion of each fin of the first portion over a first portion of the fins. A gate region is formed over a second portion of the fins. A trench is formed in a portion of the gate region. A void is formed adjacent the a portion of the gate region. A first silicon feature is formed in the trench. A second silicon feature is formed in the void. Subsequently, a replacement metal gate (RMG) process is performed in the gate region. A TS cut region is formed over the trench. The first silicon feature and the second silicon feature are removed. A metallization process is performed in the void to form a contact.

公开(公告)号：US09761452B1

公开(公告)日：2017-09-12

申请号：US15205528

申请日：2016-07-08

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jiehui Shu ,  Daniel Jaeger ,  Garo Jacques Derderian ,  Haifeng Sheng ,  Jinping Liu

IPC: H01L21/311 ,  H01L21/033 ,  H01L27/11

CPC classification number: H01L27/1116 ,  H01L21/3086 ,  H01L27/1104 ,  H01L28/00

Abstract: Devices and methods of fabricating integrated circuit devices with reduced cell height are provided. One method includes, for instance: obtaining an intermediate semiconductor device having a substrate including a logic area and an SRAM area, a fin material layer, and a hardmask layer; depositing a mandrel over the logic area; depositing a sacrificial spacer layer; etching the sacrificial spacer layer to define a sacrificial set of vertical spacers; etching the hardmask layer; leaving a set of vertical hardmask spacers; depositing a first spacer layer; etching the first spacer layer to define a first set of vertical spacers over the logic area; depositing an SOH layer; etching an opening in the SOH layer over the SRAM area; depositing a second spacer layer; and etching the second spacer layer to define a second set of spacers over the SRAM area.

公开(公告)号：US10930549B2

公开(公告)日：2021-02-23

申请号：US16573209

申请日：2019-09-17

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jinsheng Gao ,  Daniel Jaeger ,  Chih-Chiang Chang ,  Michael Aquilino ,  Patrick Carpenter ,  Junsic Hong ,  Mitchell Rutkowski ,  Haigou Huang ,  Huy Cao

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/768 ,  H01L21/28 ,  H01L21/311 ,  H01L29/417

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a cap structure and methods of manufacture. The structure includes: a gate structure composed of conductive gate material; sidewall spacers on the gate structure, extending above the conductive gate material; and a capping material on the conductive gate material and extending over the sidewall spacers on the gate structure.