公开(公告)号：US10153162B2

公开(公告)日：2018-12-11

申请号：US15284773

申请日：2016-10-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ryan Ryoung-Han Kim ,  Wenhui Wang ,  Azat Latypov ,  Tamer Coskun, Jr. ,  Lei Sun

IPC: H01L21/306 ,  H01L21/8234 ,  H01L21/027 ,  H01L21/033 ,  H01L21/308 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/66

Abstract: Methods for fabricating integrated circuits are provided. In one example, a method includes providing a circuit structure layer over a substrate and at least one etch layer over the circuit structure layer, in the at least one etch layer patterning at least one primary pattern feature having at least one primary pattern feature dimension and at least one assist pattern feature having at least one assist pattern feature dimension, where the primary pattern feature dimension is greater than the assist pattern feature dimension, reducing the at least one primary pattern feature dimension and closing the assist pattern feature to form an etch pattern, and etching a circuit structure feature using the etch pattern.

公开(公告)号：US09679809B1

公开(公告)日：2017-06-13

申请号：US15077564

申请日：2016-03-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jongwook Kye ,  Yan Wang ,  Chenchen Wang ,  Wenhui Wang ,  Lei Yuan ,  Jia Zeng ,  Guillaume Bouche

IPC: H01L21/768 ,  H01L21/311 ,  H01L21/28 ,  H01L45/00

CPC classification number: H01L21/28141 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/76816 ,  H01L45/1691

Abstract: A method of forming a pattern for interconnect lines in an integrated circuit includes providing a structure having a first lithographic stack, a mandrel layer and a pattern layer disposed over a dielectric stack. Patterning the structure to form mandrels in the mandrel layer and disposing a spacer layer over the mandrels. Etching the spacer layer to form spacers disposed on sidewalls of the mandrels. The spacers and mandrels defining beta and gamma regions. A beta region includes a beta block mask portion and a gamma region includes a gamma block mask portion of the pattern layer. The method also includes etching a beta pillar over the beta block mask portion and etching a gamma pillar over the gamma block mask portion. The method also includes etching the structure to form a pattern in the pattern layer, the pattern including the gamma and beta block mask portions.

公开(公告)号：US09595478B2

公开(公告)日：2017-03-14

申请号：US14737551

申请日：2015-06-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Wenhui Wang ,  Ryan Ryoung-han Kim ,  Linus Jang ,  Jason Cantone ,  Lei Sun ,  Seowoo Nam

IPC: H01L23/00 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/06 ,  H01L21/02 ,  H01L27/092 ,  H01L23/528

CPC classification number: H01L27/092 ,  H01L21/02126 ,  H01L21/0214 ,  H01L21/0217 ,  H01L21/3212 ,  H01L21/823828 ,  H01L21/823864 ,  H01L21/823871 ,  H01L23/528 ,  H01L27/0207 ,  H01L29/0649 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/66545

Abstract: Process of using a dummy gate as an interconnection and a method of manufacturing the same are disclosed. Embodiments include forming on a semiconductor substrate dummy gate structures at cell boundaries, each dummy gate structure including a set of sidewall spacers and a cap disposed between the sidewall spacers; removing a first sidewall spacer or at least a portion of a first cap on a first side of a first dummy gate structure and forming a first gate contact trench over the first dummy gate structure; and filling the first gate contact trench with a metal to form a first gate contact.

Abstract translation: 公开了使用虚拟栅极作为互连的工艺及其制造方法。 实施例包括在半导体衬底上形成在单元边界处的虚拟栅极结构，每个虚拟栅极结构包括一组侧壁间隔件和设置在侧壁间隔件之间的盖; 在第一伪栅极结构的第一侧上去除第一侧壁间隔物或第一盖的至少一部分，并在第一伪栅极结构上形成第一栅极接触沟槽; 以及用金属填充所述第一栅极接触沟槽以形成第一栅极接触。

公开(公告)号：US09490168B1

公开(公告)日：2016-11-08

申请号：US14710894

申请日：2015-05-13

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES, INC. ,  STMicroelectronics, Inc.

Inventor： Shyng-Tsong Chen ,  Cheng Chi ,  Chi-Chun Liu ,  Sylvie M. Mignot ,  Yann A. Mignot ,  Hosadurga K. Shobha ,  Terry A. Spooner ,  Wenhui Wang ,  Yongan Xu

IPC: H01L21/28 ,  H01L21/768 ,  H01L23/535 ,  H01L23/528

CPC classification number: H01L21/76897 ,  H01L21/76802 ,  H01L21/76811 ,  H01L21/76816 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/76885 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/5329

Abstract: A method of forming a via to an underlying layer of a semiconductor device is provided. The method may include forming a pillar over the underlying layer using a sidewall image transfer process. A dielectric layer is formed over the pillar and the underlying layer; and a via mask patterned over the dielectric layer, the via mask having a mask opening at least partially overlapping the pillar. A via opening is etched in the dielectric layer using the via mask, the mask opening defining a first lateral dimension of the via opening in a first direction and the pillar defining a second lateral dimension of the via opening in a second direction different than the first direction. The via opening is filled with a conductor to form the via. A semiconductor device and via structure are also provided.

Abstract translation: 提供了形成通孔到半导体器件的下层的方法。 该方法可以包括使用侧壁图像转移过程在下层上形成柱。 介电层形成在柱和下层之上; 以及图案化在所述电介质层上的通孔掩模，所述通孔掩模具有至少部分地与所述支柱重叠的掩模开口。 使用通孔掩模在电介质层中蚀刻通孔开口，掩模开口在第一方向上限定通孔开口的第一横向尺寸，并且柱沿不同于第一方向的第二方向限定通孔开口的第二横向尺寸 方向。 通孔开口填充有导体以形成通孔。 还提供了半导体器件和通孔结构。

公开(公告)号：US20160358820A1

公开(公告)日：2016-12-08

申请号：US15239178

申请日：2016-08-17

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES, INC. ,  STMicroelectronics, Inc.

Inventor： Shyng-Tsong Chen ,  Cheng Chi ,  Chi-Chun Liu ,  Sylvie M. Mignot ,  Yann A. Mignot ,  Hosadurga K. Shobha ,  Terry A. Spooner ,  Wenhui Wang ,  Yongan Xu

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L21/76897 ,  H01L21/76802 ,  H01L21/76811 ,  H01L21/76816 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/76885 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/5329

Abstract: A method of forming a via to an underlying layer of a semiconductor device is provided. The method may include forming a pillar over the underlying layer using a sidewall image transfer process. A dielectric layer is formed over the pillar and the underlying layer; and a via mask patterned over the dielectric layer, the via mask having a mask opening at least partially overlapping the pillar. A via opening is etched in the dielectric layer using the via mask, the mask opening defining a first lateral dimension of the via opening in a first direction and the pillar defining a second lateral dimension of the via opening in a second direction different than the first direction. The via opening is filled with a conductor to form the via. A semiconductor device and via structure are also provided.

Abstract translation: 提供了形成通孔到半导体器件的下层的方法。 该方法可以包括使用侧壁图像转移过程在下层上形成柱。 介电层形成在柱和下层之上; 以及图案化在所述电介质层上的通孔掩模，所述通孔掩模具有至少部分地与所述支柱重叠的掩模开口。 使用通孔掩模在电介质层中蚀刻通孔开口，掩模开口在第一方向上限定通孔开口的第一横向尺寸，并且柱沿不同于第一方向的第二方向限定通孔开口的第二横向尺寸 方向。 通孔开口填充有导体以形成通孔。 还提供了半导体器件和通孔结构。

公开(公告)号：US09484258B1

公开(公告)日：2016-11-01

申请号：US15071247

申请日：2016-03-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ryan Ryoung-han Kim ,  Wenhui Wang ,  Lei Sun ,  Erik Verduijn ,  Yulu Chen

IPC: H01L21/768 ,  H01L23/528

CPC classification number: H01L21/76897 ,  H01L21/31144 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76816 ,  H01L23/5226 ,  H01L23/528

Abstract: A method for producing self-aligned vias (SAV) is provided. Embodiments include forming a ILOS layer over a dielectric layer; forming pairs of spacers over the ILOS layer, each pair of spacers having a first filler formed between adjacent spacers, and a second filler formed between each pair of spacers; forming and patterning a first OPL to expose one second filler, spacers on opposite sides of the one second filler, and a portion of the first filler adjacent each of the exposed spacers; removing the one second filler to form a SAV, and SAV etching into the ILOS layer; forming a second OPL over the first OPL and in the SAV to form a SAV plug; removing OPL layers and etching into the ILOS layer down to the dielectric layer; forming a third OPL layer in spaces between the TEOS layer; and removing the SAV plug.

Abstract translation: 提供了一种生产自对准通孔（SAV）的方法。 实施例包括在电介质层上形成ILOS层; 在ILOS层上形成隔离物对，每对隔离物具有形成在相邻间隔物之间​​的第一填料和在每对隔离物之间形成的第二填料; 形成和图案化第一OPL以暴露一个第二填料，一个第二填料的相对侧上的间隔物和与每个暴露间隔物相邻的第一填料的一部分; 去除一个第二填料以形成SAV，并且SAV蚀刻到ILOS层中; 在第一OPL和SAV上形成第二OPL以形成SAV插头; 去除OPL层并蚀刻到ILOS层中直到电介质层; 在TEOS层之间的空间中形成第三OPL层; 并卸下SAV插头。

公开(公告)号：US09478462B1

公开(公告)日：2016-10-25

申请号：US15071255

申请日：2016-03-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Wenhui Wang ,  Ryan Ryoung-han Kim ,  Lei Sun ,  Erik Verduijn ,  Yulu Chen

IPC: H01L21/768 ,  H01L21/306 ,  H01L21/311 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L21/76816 ,  H01L21/76808 ,  H01L21/76897 ,  H01L23/5226

Abstract: Methods of forming a SAV using a selective SAQP or SADP process are provided. Embodiments include providing on a TiN layer and dielectric layers alternating mandrels and non-mandrel fillers, spacers therebetween, and a metal cut plug through a mandrel or a non-mandrel filler; removing a non-mandrel filler through a SAV patterning stack having an opening over the non-mandrel filler and adjacent spacers, forming a trench; removing a mandrel through a second SAV patterning stack having an opening over the mandrel and adjacent spacers, forming a second trench; etching the trenches through the TiN and dielectric layers; forming plugs in the trenches; removing the mandrels and non-mandrel fillers, forming third trenches; etching the third trenches through the TiN layer; removing the metal cut plug and spacers and etching the third trenches into the dielectric layer; removing the plugs; and filling the trenches with metal.

Abstract translation: 提供了使用选择性SAQP或SADP方法形成SAV的方法。 实施例包括在TiN层和介电层上提供交替的心轴和非心轴填料，间隔件和通过心轴或非心轴填料的金属切割塞; 通过具有在非芯棒填料和相邻间隔物上的开口的SAV图案化叠层去除非芯棒填料，形成沟槽; 通过具有在所述心轴和相邻间隔物上的开口的第二SAV图案化叠层移除心轴，形成第二沟槽; 通过TiN和电介质层蚀刻沟槽; 在沟槽中形成插塞; 去除心轴和非心轴填料，形成第三沟槽; 蚀刻通过TiN层的第三沟槽; 去除金属切割塞子和间隔件并将第三沟槽蚀刻到介电层中; 取下插头; 并用金属填充沟槽。

公开(公告)号：US20150129934A1

公开(公告)日：2015-05-14

申请号：US14079159

申请日：2013-11-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Vimal K. Kamineni ,  Abner F. Bello ,  Nicholas V. LiCausi ,  Wenhui Wang ,  Michael Wedlake ,  Jason R. Cantone

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/165 ,  H01L21/8234

CPC classification number: H01L29/785 ,  H01L21/02164 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/308 ,  H01L21/32133 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/10879 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/1033 ,  H01L29/165 ,  H01L29/51 ,  H01L29/66545 ,  H01L29/66787 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/7843 ,  H01L29/7846 ,  H01L2029/7858

Abstract: One method disclosed includes performing a selective etching process through a gate cavity to selectively remove a portion of a first semiconductor material relative to a second layer of a second semiconductor material and a substrate so as to thereby define a space between the second semiconducting material and the substrate, filling substantially all of the space with an insulating material so as to thereby define a substantially self-aligned channel isolation region positioned under at least what will become the channel region of the FinFET device.

Abstract translation: 所公开的一种方法包括通过栅极腔执行选择性蚀刻工艺，以相对于第二半导体材料和衬底的第二层选择性地去除第一半导体材料的一部分，从而限定第二半导体材料与第二半导体材料之间的空间 衬底，用绝缘材料填充基本上所有的空间，从而限定位于至少将成为FinFET器件的沟道区的至少自对准沟道隔离区。

公开(公告)号：US10347546B2

公开(公告)日：2019-07-09

申请号：US15389632

申请日：2016-12-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jia Zeng ,  Wenhui Wang ,  Xuelian Zhu ,  Jongwook Kye

IPC: H01L23/528 ,  H01L23/532 ,  H01L29/06 ,  H01L29/08 ,  H01L27/105 ,  H01L27/108 ,  H01L27/112 ,  H01L21/84 ,  H01L27/12 ,  H01L23/485 ,  H01L21/82 ,  H01L21/8234 ,  H01L27/088

Abstract: The disclosure relates to integrated circuit (IC) structures with substantially T-shaped wires, and methods of forming the same. An IC structure according to the present disclosure can include a first substantially T-shaped wire including a first portion extending in a first direction, and a second portion extending in a second direction substantially perpendicular to the first direction; an insulator laterally abutting the first substantially T-shaped wire at an end of the first portion, opposite the second portion; and a pair of gates each extending in the first direction and laterally abutting opposing sidewalls of the insulator and the first portion of the substantially T-shaped wire.

公开(公告)号：US10204861B2

公开(公告)日：2019-02-12

申请号：US15399200

申请日：2017-01-05

Applicant: GLOBALFOUNDRIES INC.

Inventor： Xuelian Zhu ,  Jia Zeng ,  Wenhui Wang ,  Youngtag Woo ,  Jongwook Kye

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L23/535 ,  H01L29/417 ,  H01L21/768

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to contacts for local connections and methods of manufacture. The structure includes: at least one contact electrically shorted to a gate structure and a source/drain contact and located below a first wiring layer; and gate, source and drain contacts extending from selected gate structures and electrically connecting to the first wiring layer.