PHOTONICS CHIP
    13.
    发明申请

    公开(公告)号:US20170261693A1

    公开(公告)日:2017-09-14

    申请号:US15068059

    申请日:2016-03-11

    CPC classification number: G02B6/34 G02B6/124 G02B6/13 G02B6/30

    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to photonics chips and methods of manufacture. A structure includes: a photonics chip having a grated optical coupler; an interposer attached to the photonics chip, the interposer having a grated optical coupler; an optical epoxy material provided between the grated optical coupler of the photonics chip and the grated optical coupler of the interposer; and epoxy underfill material provided at interstitial regions between the photonics chip and the interposer which lie outside of an area of the grated optical couplers of the photonics chip and the interposer.

    INTERCONNECTED INTEGRATED CIRCUIT (IC) CHIP STRUCTURE AND PACKAGING AND METHOD OF FORMING SAME

    公开(公告)号:US20190287879A1

    公开(公告)日:2019-09-19

    申请号:US15921852

    申请日:2018-03-15

    Abstract: An IC chip structure including a plurality of IC chips electrically connected to one another in back-end-of-line (BEOL) interconnect layer of the structure is disclosed. The IC structure may include openings in crack-stop structures surrounding the IC chips and a interconnect wire extending between the IC chips through the openings. A packaging structure for utilizing the IC structure where at least one IC chip is inoperable is also disclosed. The structure may include a first bond pad array on a top surface of a packaging substrate including operable bond pads connected to an operable IC chip and structural support bond pads connected to the inoperable IC chip; a second bond pad array on a bottom surface of the substrate including operable bond pads connected to a single IC chip printed circuit board; and an interconnect structure for connecting the operable bond pads of the first and second bond pad arrays.

    Semiconductor test wafer and methods for use thereof
    17.
    发明授权
    Semiconductor test wafer and methods for use thereof 有权
    半导体测试晶片及其使用方法

    公开(公告)号:US09257352B2

    公开(公告)日:2016-02-09

    申请号:US13835358

    申请日:2013-03-15

    CPC classification number: H01L22/34

    Abstract: A test wafer is disclosed with a first side configured to have integrated circuits formed thereon and a second side with a test structure formed thereon. The test wafer can include electrical test structures embedded in the second side of the wafer. An electrical test of the test wafer can be performed after handling by a tool used in a wafer manufacturing process to determine if the tool caused a defect on the second side of the wafer. The test structure can include a blanket layer disposed on the second side of the wafer. The test wafer can then be exposed to a wet etch and inspected thereafter for the presence of an ingress path caused from the etch chemistry. The presence of an ingress path is an indication that the tool used prior to the wet etch caused a defect in the wafer.

    Abstract translation: 公开了一种测试晶片,其第一侧被配置为具有形成在其上的集成电路,以及形成有测试结构的第二侧。 测试晶片可以包括嵌入晶片第二侧的电测试结构。 测试晶片的电气测试可以在通过晶片制造过程中使用的工具处理之后进行,以确定工具是否在晶片的第二侧引起缺陷。 测试结构可以包括布置在晶片的第二侧上的覆盖层。 然后可以将测试晶片暴露于湿蚀刻,然后检查是否存在由蚀刻化学物质引起的入口路径。 进入路径的存在表示在湿蚀刻之前使用的工具导致晶片中的缺陷。

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