公开(公告)号：US10049897B2

公开(公告)日：2018-08-14

申请号：US15421737

申请日：2017-02-01

Applicant: GLOBALFOUNDRIES INC.

Inventor： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter ,  Timothy D. Sullivan

IPC: H01L21/306 ,  H01L23/498 ,  H01L21/56 ,  H01L23/31 ,  H01L23/00

Abstract: Various embodiments include methods of forming interconnect structures, and the structures formed by such methods. In one embodiment, an interconnect structure can include: a photosensitive polyimide (PSPI) layer including a pedestal portion; a controlled collapse chip connection (C4) bump overlying the pedestal portion of the PSPI layer; a solder overlying the C4 bump and contacting a side of the C4 bump; and an underfill layer abutting the pedestal portion of the PSPI and the C4 bump, wherein the underfill layer and the solder form a first interface separated from the PSPI pedestal.

公开(公告)号：US09875956B1

公开(公告)日：2018-01-23

申请号：US15276182

申请日：2016-09-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： Wolfgang Sauter ,  Mark W. Kuemerle ,  Daniel P. Greenberg ,  Eric W. Tremble

IPC: H01L23/52 ,  H01L23/498 ,  H01L23/66 ,  H01L25/065 ,  H01L23/00

CPC classification number: H01L23/49816 ,  H01L23/49838 ,  H01L23/66 ,  H01L24/04 ,  H01L24/14 ,  H01L25/0657 ,  H01L2223/6644 ,  H01L2223/6688 ,  H01L2224/0401 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2224/14131 ,  H01L2224/14134 ,  H01L2224/14177 ,  H01L2225/06513 ,  H01L2225/06517

Abstract: The present disclosure relates to interface structures and, more particularly, to integrated interface structures with both parallel and serial interfaces and methods of manufacture. The integrated interface structure includes: a substrate; a plurality of serial interface connections integrated on the substrate; and a plurality of parallel interface connections on the integrated substrate and within spaces between sets of the plurality of serial interface connections.

公开(公告)号：US20170261693A1

公开(公告)日：2017-09-14

申请号：US15068059

申请日：2016-03-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jeffery P. GAMBINO ,  Wolfgang Sauter ,  Christopher D. MUZZY ,  Charles L. ARVIN ,  Robert LEIDY

IPC: G02B6/34 ,  G02B6/124 ,  G02B6/13 ,  G02B6/30

CPC classification number: G02B6/34 ,  G02B6/124 ,  G02B6/13 ,  G02B6/30

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to photonics chips and methods of manufacture. A structure includes: a photonics chip having a grated optical coupler; an interposer attached to the photonics chip, the interposer having a grated optical coupler; an optical epoxy material provided between the grated optical coupler of the photonics chip and the grated optical coupler of the interposer; and epoxy underfill material provided at interstitial regions between the photonics chip and the interposer which lie outside of an area of the grated optical couplers of the photonics chip and the interposer.

公开(公告)号：US20190287879A1

公开(公告)日：2019-09-19

申请号：US15921852

申请日：2018-03-15

Applicant: GLOBALFOUNDRIES INC.

Inventor： Wolfgang Sauter ,  Mark W. Kuemerle ,  Eric W. Tremble ,  David B. Stone ,  Nicholas A. Polomoff ,  Eric S. Parent ,  Jawahar P. Nayak ,  Seungman Choi

IPC: H01L23/488 ,  H01L25/065

Abstract: An IC chip structure including a plurality of IC chips electrically connected to one another in back-end-of-line (BEOL) interconnect layer of the structure is disclosed. The IC structure may include openings in crack-stop structures surrounding the IC chips and a interconnect wire extending between the IC chips through the openings. A packaging structure for utilizing the IC structure where at least one IC chip is inoperable is also disclosed. The structure may include a first bond pad array on a top surface of a packaging substrate including operable bond pads connected to an operable IC chip and structural support bond pads connected to the inoperable IC chip; a second bond pad array on a bottom surface of the substrate including operable bond pads connected to a single IC chip printed circuit board; and an interconnect structure for connecting the operable bond pads of the first and second bond pad arrays.

公开(公告)号：US09798088B2

公开(公告)日：2017-10-24

申请号：US14933668

申请日：2015-11-05

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jeffrey P. Gambino ,  Robert K. Leidy ,  Wolfgang Sauter ,  Christopher D. Muzzy ,  Eric Turcotte ,  Thomas E. Lombardi

IPC: G02B6/30 ,  G02B6/13

CPC classification number: G02B6/30 ,  G02B6/13 ,  G02B6/4239 ,  G02B6/4243 ,  G02B6/428

Abstract: The disclosure relates to semiconductor structures and, more particularly, to barrier structures for underfill blockout regions uses in phonotics chip packaging and methods of manufacture. The structure includes a substrate with a plurality of solder connections and at least one optical fiber interface disposed within at least one cavity of the substrate. The structure further includes a barrier structure formed about the cavity which is structured to prevent underfill material from degrading an optical coupling of the optical fiber.

公开(公告)号：US09397054B2

公开(公告)日：2016-07-19

申请号：US14876889

申请日：2015-10-07

Applicant: GLOBALFOUNDRIES INC.

Inventor： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter

IPC: H01L23/48 ,  H01L23/00 ,  H01L21/768 ,  H01L23/31 ,  H01L23/58 ,  H01L23/522

CPC classification number: H01L23/562 ,  H01L21/76802 ,  H01L21/76843 ,  H01L21/76871 ,  H01L21/76877 ,  H01L23/3114 ,  H01L23/3192 ,  H01L23/481 ,  H01L23/522 ,  H01L23/585 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02126 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/03462 ,  H01L2224/0347 ,  H01L2224/0348 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05186 ,  H01L2224/05568 ,  H01L2224/0558 ,  H01L2224/1134 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13009 ,  H01L2224/13023 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/94 ,  H01L2924/01029 ,  H01L2924/01073 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/12042 ,  H01L2924/15788 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/11 ,  H01L2224/03

Abstract: A semiconductor structure with an interconnect level above a substrate and including a conductive pad and a metallic structure, such as a base of a crackstop. A first dielectric layer is above the conductive pad and above the metallic structure. A first opening in the first dielectric layer is aligned with and exposes the conductive pad and a second opening is aligned with and exposes the metallic structure. A metallic liner lines the first opening and the second opening and is on the top surface of the first dielectric layer. A second dielectric layer is above the metallic liner and a third dielectric layer is above the second dielectric layer. A third opening exposes a portion of the metal liner above the conductive pad and a copper plug and pedestal are in the third opening on the exposed portion of the metal liner.

Abstract translation: 一种半导体结构，其具有在衬底上方的互连水平并且包括导电焊盘和金属结构，例如裂缝挡板的基部。 第一介电层位于导电焊盘的上方，并在金属结构之上。 第一介电层中的第一开口与导电焊盘对准并且暴露，并且第二开口与金属结构对准并且暴露出金属结构。 金属衬垫将第一开口和第二开口线排列在第一介电层的顶表面上。 第二电介质层在金属衬垫之上，第三电介质层位于第二电介质层之上。 第三个开口将金属衬垫的一部分暴露在导电垫的上方，铜插头和基座位于金属衬垫的暴露部分的第三个开口中。

公开(公告)号：US09257352B2

公开(公告)日：2016-02-09

申请号：US13835358

申请日：2013-03-15

Applicant: GLOBALFOUNDRIES INC.

Inventor： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter

IPC: G01R31/02 ,  G01R31/26 ,  H01L21/66

CPC classification number: H01L22/34

Abstract: A test wafer is disclosed with a first side configured to have integrated circuits formed thereon and a second side with a test structure formed thereon. The test wafer can include electrical test structures embedded in the second side of the wafer. An electrical test of the test wafer can be performed after handling by a tool used in a wafer manufacturing process to determine if the tool caused a defect on the second side of the wafer. The test structure can include a blanket layer disposed on the second side of the wafer. The test wafer can then be exposed to a wet etch and inspected thereafter for the presence of an ingress path caused from the etch chemistry. The presence of an ingress path is an indication that the tool used prior to the wet etch caused a defect in the wafer.

Abstract translation: 公开了一种测试晶片，其第一侧被配置为具有形成在其上的集成电路，以及形成有测试结构的第二侧。 测试晶片可以包括嵌入晶片第二侧的电测试结构。 测试晶片的电气测试可以在通过晶片制造过程中使用的工具处理之后进行，以确定工具是否在晶片的第二侧引起缺陷。 测试结构可以包括布置在晶片的第二侧上的覆盖层。 然后可以将测试晶片暴露于湿蚀刻，然后检查是否存在由蚀刻化学物质引起的入口路径。 进入路径的存在表示在湿蚀刻之前使用的工具导致晶片中的缺陷。