公开(公告)号：US20170365676A1

公开(公告)日：2017-12-21

申请号：US15590459

申请日：2017-05-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xusheng WU ,  Haigou HUANG

IPC: H01L29/423 ,  H01L29/40 ,  H01L27/088 ,  H01L29/06 ,  H01L29/51 ,  H01L29/49

CPC classification number: H01L29/42356 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/401 ,  H01L29/4991 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: Devices and methods of fabricating integrated circuit devices for increasing performance through gate cut last processes are provided. One method includes, for instance: obtaining an intermediate semiconductor device having a substrate including a plurality of fins, an STI layer, an oxide layer, and a gate material over the oxide layer, the fins extending into the gate material; removing the gate material and the oxide layer; depositing a high k material on a top surface of the STI layer, surrounding the fins; depositing a gate stack over the high k material; filling the top of the device with a gate contact metal; etching a portion of the gate contact metal, the metal gate stack, and the high k material; and filling the portion with an inter-layer dielectric. Also disclosed is an intermediate device formed by the method.

公开(公告)号：US20170213890A1

公开(公告)日：2017-07-27

申请号：US15482086

申请日：2017-04-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xusheng WU ,  Jin Ping LIU ,  Min-hwa CHI

IPC: H01L29/165 ,  H01L29/08 ,  H01L29/737 ,  H01L29/78 ,  H01L21/265 ,  H01L29/66

CPC classification number: H01L29/165 ,  H01L21/26506 ,  H01L29/0821 ,  H01L29/0847 ,  H01L29/66242 ,  H01L29/6625 ,  H01L29/66272 ,  H01L29/66636 ,  H01L29/732 ,  H01L29/737 ,  H01L29/7371 ,  H01L29/7848

Abstract: Transistor structures and methods of fabricating transistor structures are provided. The methods include: fabricating a transistor structure at least partially within a substrate, the fabricating including: providing a cavity within the substrate; and forming a first portion and a second portion of the transistor structure at least partially within the cavity, the first portion being disposed at least partially between the substrate and the second portion, where the first portion inhibits diffusion of material from the second portion into the substrate. In one embodiment, the transistor structure is a field-effect transistor structure, and the first portion and the second portion include one of a source region or a drain region of the field-effect transistor structure. In another embodiment, the transistor structure is a bipolar junction transistor structure.

公开(公告)号：US20160322348A1

公开(公告)日：2016-11-03

申请号：US15140618

申请日：2016-04-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xusheng WU

IPC: H01L27/06 ,  H01L29/167 ,  H01L29/423 ,  H01L29/78 ,  H01L29/06 ,  H01L29/417

CPC classification number: H01L27/0629 ,  H01L21/26513 ,  H01L21/2658 ,  H01L21/266 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/0255 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/167 ,  H01L29/41791 ,  H01L29/42372 ,  H01L29/6609 ,  H01L29/66136 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/7851 ,  H01L29/861

Abstract: Methods for preparing a FinFET device with a protection diode formed prior to M1 formation and resulting devices are disclosed. Embodiments include forming plural fins on a substrate, with a STI region between adjacent fins; forming a dummy gate stack over and perpendicular to the fins, the gate stack including a dummy gate over a dummy gate insulating layer; forming sidewall spacers on opposite sides of the dummy gate stack; forming source/drain regions at opposite sides of the dummy gate stack; forming an ILD over the STI regions between fins; removing the dummy gate stack forming a gate cavity; forming a gate dielectric in the gate cavity; removing the gate dielectric from the gate cavity in a protection diode area, exposing an underlying fin; implanting a dopant into the exposed fin; and forming a RMG in the gate cavity, wherein a protection diode is formed in the protection diode area.

Abstract translation: 公开了在形成M1形成之前形成保护二极管的FinFET器件的制备方法。 实施例包括在基板上形成多个翅片，其中在相邻翅片之间具有STI区域; 在所述散热片上方形成虚拟栅极堆叠并且垂直于所述散热片，所述栅极堆叠包括虚拟栅极绝缘层上的伪栅极; 在所述伪栅极堆叠的相对侧上形成侧壁间隔物; 在虚拟栅极堆叠的相对侧形成源极/漏极区域; 在翅片之间的STI区域上形成ILD; 去除形成门腔的虚拟栅极堆叠; 在栅腔中形成栅极电介质; 在保护二极管区域中从栅极腔去除栅极电介质，暴露下面的鳍; 将掺杂剂注入暴露的翅片中; 以及在所述栅极腔中形成RMG，其中在所述保护二极管区域中形成保护二极管。

公开(公告)号：US20160118500A1

公开(公告)日：2016-04-28

申请号：US14523548

申请日：2014-10-24

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Xusheng WU ,  Min-hwa CHI ,  Edmund Kenneth BANGHART

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L21/3065 ,  H01L21/266 ,  H01L21/306 ,  H01L21/308 ,  H01L29/66 ,  H01L21/265

CPC classification number: H01L29/66537 ,  H01L29/0653 ,  H01L29/1033 ,  H01L29/1083 ,  H01L29/16 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/66818 ,  H01L29/7851 ,  H01L29/7853

Abstract: A method of forming a FinFET fin with low-doped and a highly-doped active portions and/or a FinFET fin having tapered sidewalls for Vt tuning and multi-Vt schemes and the resulting device are provided. Embodiments include forming an Si fin, the Si fin having a top active portion and a bottom active portion; forming a hard mask on a top surface of the Si fin; forming an oxide layer on opposite sides of the Si fin; implanting a dopant into the Si fin; recessing the oxide layer to reveal the active top portion of the Si fin; etching the top active portion of the Si fin to form vertical sidewalls; forming a nitride spacer covering each vertical sidewall; recessing the recessed oxide layer to reveal the active bottom portion of the Si fin; and tapering the active bottom portion of the Si fin.

Abstract translation: 提供一种形成具有低掺杂和高掺杂有源部分的FinFET鳍片的方法和/或具有用于Vt调谐和多Vt方案的锥形侧壁的FinFET鳍片以及所得到的器件。 实施例包括形成Si翅片，所述Si翅片具有顶部活性部分和底部活性部分; 在Si翅片的顶表面上形成硬掩模; 在所述Si翅片的相对侧上形成氧化物层; 将掺杂剂注入到Si鳍中; 凹陷氧化物层以露出Si鳍的有效顶部; 蚀刻Si翅片的顶部活性部分以形成垂直侧壁; 形成覆盖每个垂直侧壁的氮化物间隔物; 凹陷凹陷的氧化物层以露出Si鳍的活性底部; 并使Si翅片的活性底部部分变细。

公开(公告)号：US20150340501A1

公开(公告)日：2015-11-26

申请号：US14285042

申请日：2014-05-22

Applicant: GLOBALFOUNDRIES INC.

Inventor： Xusheng WU ,  Johannes Marinus VAN MEER ,  Manfred ELLER ,  Vara Govindeswara Reddy VAKADA

IPC: H01L29/78 ,  H01L21/265 ,  H01L29/66

CPC classification number: H01L21/26586 ,  H01L21/26506 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/66484 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/7847 ,  H01L29/785 ,  H01L29/7855

Abstract: Methods for producing independent-gate FinFETs with improved channel mobility and the resulting devices are disclosed. Embodiments may include forming an independent-gate fin field-effect transistor (FinFET) above a substrate; and forming stress within the fin between two independent gates of the independent-gate FinFET.

Abstract translation: 公开了用于制造具有改善的沟道迁移率的独立栅极FinFET和所得到的器件的方法。 实施例可以包括在衬底上形成独立栅极鳍效应晶体管（FinFET）; 并在独立栅极FinFET的两个独立栅极之间的鳍内形成应力。

公开(公告)号：US20150332972A1

公开(公告)日：2015-11-19

申请号：US14279480

申请日：2014-05-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xusheng WU ,  Jianwei PENG ,  Min-hwa CHI

IPC: H01L21/8234 ,  H01L21/02

CPC classification number: H01L21/823431 ,  H01L21/02521 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/823437 ,  H01L21/823475

Abstract: A method of fabricating a raised fin structure including a raised contact structure is provided. The method may include: providing a base fin structure; providing at least one ancillary fin structure, the at least one ancillary fin structure contacting the base fin structure at a side of the base fin structure; growing a material over the base fin structure to form the raised fin structure; and, growing the material over the at least one ancillary fin structure, wherein the at least one ancillary fin structure contacting the base fin structure increases a volume of material grown over the base fin structure near the contact between the base fin structure and the at least one ancillary fin structure to form the raised contact structure.

Abstract translation: 提供了一种制造包括凸起接触结构的凸起鳍结构的方法。 该方法可以包括：提供底鳍结构; 提供至少一个辅助翅片结构，所述至少一个辅助翅片结构在所述基部翅片结构的一侧与所述底部翅片结构接触; 在基板结构上生长材料以形成凸起的翅片结构; 并且在所述至少一个辅助翅片结构上生长所述材料，其中所述至少一个辅助翅片结构接触所述基底翅片结构增加了在所述基底翅片结构与所述至少 一个辅助翅片结构形成凸起的接触结构。

公开(公告)号：US20190115426A1

公开(公告)日：2019-04-18

申请号：US15786284

申请日：2017-10-17

Applicant: GLOBALFOUNDRIES INC.

Inventor： Chun Yu WONG ,  Hui ZANG ,  Xusheng WU

IPC: H01L29/06 ,  H01L27/088 ,  H01L29/161 ,  H01L21/8234 ,  H01L29/66

CPC classification number: H01L29/0653 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/161 ,  H01L29/66545

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to fin structures with single diffusion break facet improvement using an epitaxial insulator and methods of manufacture. The structure includes: a plurality of fin structures; an insulator material filling a cut between adjacent fin structures of the plurality of fin structures; a metal material (e.g., rare earth oxide or SrTiO3) at least partially lining the cut; and an epitaxial source region or epitaxial drain region in at least one of the plurality of fin structures and adjacent to the metal material.

公开(公告)号：US20170256541A1

公开(公告)日：2017-09-07

申请号：US15599751

申请日：2017-05-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xusheng WU ,  Qizhi LIU ,  David HARAME ,  Renata Camillo-Castillo

IPC: H01L27/088 ,  H01L21/308 ,  H01L21/311 ,  H01L21/324 ,  H01L21/8234 ,  H01L21/02

CPC classification number: H01L21/324 ,  H01L21/823821 ,  H01L21/823892 ,  H01L29/66803

Abstract: A method of making a semiconductor structure is provided including providing a plurality of fins on a semiconductor substrate; depositing a layer containing silicon dioxide on the plurality of fins and on a surface of the semiconductor substrate; depositing a photoresist layer on one or more but less than all of the plurality of fins; etching the layer of silicon dioxide off of one or more of the plurality of fins on which the photoresist layer had not been deposited; stripping the photoresist layer; depositing a layer of pure boron on one or more of the plurality of fins on which a photoresist had not been deposited; and depositing a silicon nitride liner step on the plurality of fins. A partial semiconductor device fabricated by said method is also provided.

公开(公告)号：US20170222015A1

公开(公告)日：2017-08-03

申请号：US15490180

申请日：2017-04-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： George Robert MULFINGER ,  Xusheng WU

IPC: H01L29/49 ,  H01L29/66 ,  H01L29/08 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L29/4983 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/6656 ,  H01L29/66575 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/7838 ,  H01L29/786 ,  H01L29/78654

Abstract: A method of controlling the facet height of raised source/drain epi structures using multiple spacers, and the resulting device are provided. Embodiments include providing a gate structure on a SOI layer; forming a first pair of spacers on the SOI layer adjacent to and on opposite sides of the gate structure; forming a second pair of spacers on an upper surface of the first pair of spacers adjacent to and on the opposite sides of the gate structure; and forming a pair of faceted raised source/drain structures on the SOI, each of the faceted source/drain structures faceted at the upper surface of the first pair of spacers, wherein the second pair of spacers is more selective to epitaxial growth than the first pair of spacers.

公开(公告)号：US20160322384A1

公开(公告)日：2016-11-03

申请号：US14700748

申请日：2015-04-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui ZANG ,  Bingwu LIU ,  Xusheng WU

IPC: H01L27/12 ,  H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L29/73 ,  H01L29/08 ,  H01L21/84 ,  H01L21/02

CPC classification number: H01L29/0684 ,  H01L21/8249 ,  H01L21/84 ,  H01L27/0623 ,  H01L27/1207 ,  H01L29/0847 ,  H01L29/66242 ,  H01L29/66272 ,  H01L29/66568 ,  H01L29/732 ,  H01L29/7371 ,  H01L29/78

Abstract: A method can include epitaxially growing epitaxial growth material within a logic region of a semiconductor structure. A method can include performing simultaneously with the growing epitaxial growth within an analog region of the semiconductor structure. A method can include performing epitaxial growth to form an epitaxial growth formation that defines an electrode of an analog device within an analog region of the semiconductor structure, wherein the performing includes using a first surface and a second surface as seed surfaces.

Abstract translation: 一种方法可以包括在半导体结构的逻辑区域内外延生长外延生长材料。 一种方法可以包括与半导体结构的模拟区域内的增长的外延生长同时执行。 一种方法可以包括进行外延生长以形成限定半导体结构的模拟区域内的模拟器件的电极的外延生长结构，其中执行包括使用第一表面和第二表面作为晶种表面。