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公开(公告)号：US09706656B2
公开(公告)日：2017-07-11
申请号：US14950584
申请日：2015-11-24
Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
Inventor： Chien-Min Hsu , Shih-Hsien Wu , Jing-Yao Chang , Tao-Chih Chang , Ren-Shin Cheng , Min-Lin Lee
CPC classification number: H05K1/116 , H05K1/0251 , H05K3/42 , H05K2201/0187 , H05K2201/09545 , H05K2203/1105 , H05K2203/1178 , H05K2203/143 , H05K2203/1438
Abstract: A signal transmission board includes a substrate, a conductive via, a cavity and a connecting hole. The substrate has a first external surface and a second external surface. The conductive via penetrating through the substrate has a first end and a second end. The first end is disposed on the first external surface, and the second end is disposed on the second external surface. The cavity is disposed in the substrate and penetrated by the conductive via. The connecting hole disposed on the substrate has a third end and a fourth end. The third end is disposed on the first external surface, and the fourth end communicates with the cavity.
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公开(公告)号：US09484315B2
公开(公告)日：2016-11-01
申请号：US14668994
申请日：2015-03-26
Applicant: Industrial Technology Research Institute
Inventor： Yu-Min Lin , Po-Chen Lin , Jing-Yao Chang
IPC: H01L23/498 , H01L23/00
CPC classification number: H01L24/08 , H01L24/05 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/73 , H01L2224/02166 , H01L2224/04042 , H01L2224/05082 , H01L2224/05124 , H01L2224/05147 , H01L2224/05155 , H01L2224/05582 , H01L2224/05624 , H01L2224/05647 , H01L2224/05655 , H01L2224/05664 , H01L2224/32225 , H01L2224/45015 , H01L2224/45124 , H01L2224/45147 , H01L2224/4801 , H01L2224/48455 , H01L2224/4847 , H01L2224/73265 , H01L2924/00014 , H01L2924/13055 , H01L2924/13091 , H01L2924/2076 , H01L2924/00015 , H01L2224/29099
Abstract: A chip structure includes a chip, a first metal layer, a second metal layer and a bonding wire. The first metal layer is disposed on the chip, and a material of the first metal layer includes nickel or nickel alloy. The second metal layer is disposed on the first metal layer, and a material of the second metal layer includes copper, copper alloy, aluminum, aluminum alloy, palladium or palladium alloy. The bonding wire is connected to the second metal layer, and a material of the bonding wire includes copper or copper alloy.
Abstract translation: 芯片结构包括芯片，第一金属层，第二金属层和接合线。 第一金属层设置在芯片上，第一金属层的材料包括镍或镍合金。 第二金属层设置在第一金属层上，第二金属层的材料包括铜，铜合金，铝，铝合金，钯或钯合金。 接合线与第二金属层连接，接合线的材料包括铜或铜合金。
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公开(公告)号：US20160163665A1
公开(公告)日：2016-06-09
申请号：US14668994
申请日：2015-03-26
Applicant: Industrial Technology Research Institute
Inventor： Yu-Min Lin , Po-Chen Lin , Jing-Yao Chang
IPC: H01L23/00
CPC classification number: H01L24/08 , H01L24/05 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/73 , H01L2224/02166 , H01L2224/04042 , H01L2224/05082 , H01L2224/05124 , H01L2224/05147 , H01L2224/05155 , H01L2224/05582 , H01L2224/05624 , H01L2224/05647 , H01L2224/05655 , H01L2224/05664 , H01L2224/32225 , H01L2224/45015 , H01L2224/45124 , H01L2224/45147 , H01L2224/4801 , H01L2224/48455 , H01L2224/4847 , H01L2224/73265 , H01L2924/00014 , H01L2924/13055 , H01L2924/13091 , H01L2924/2076 , H01L2924/00015 , H01L2224/29099
Abstract: A chip structure includes a chip, a first metal layer, a second metal layer and a bonding wire. The first metal layer is disposed on the chip, and a material of the first metal layer includes nickel or nickel alloy. The second metal layer is disposed on the first metal layer, and a material of the second metal layer includes copper, copper alloy, aluminum, aluminum alloy, palladium or palladium alloy. The bonding wire is connected to the second metal layer, and a material of the bonding wire includes copper or copper alloy.
Abstract translation: 芯片结构包括芯片，第一金属层，第二金属层和接合线。 第一金属层设置在芯片上，第一金属层的材料包括镍或镍合金。 第二金属层设置在第一金属层上，第二金属层的材料包括铜，铜合金，铝，铝合金，钯或钯合金。 接合线与第二金属层连接，接合线的材料包括铜或铜合金。
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公开(公告)号：US20130168798A1
公开(公告)日：2013-07-04
申请号：US13727599
申请日：2012-12-27
Applicant: Industrial Technology Research Institute
Inventor： Jing-Yao Chang , Tao-Chih Chang , Yu-Wei Huang , Yu-Min Lin , Shin-Yi Huang
IPC: H01L25/16
CPC classification number: H01L25/16 , H01L23/3121 , H01L23/38 , H01L24/16 , H01L24/32 , H01L24/48 , H01L24/73 , H01L25/0657 , H01L2224/16145 , H01L2224/32225 , H01L2224/48227 , H01L2224/73253 , H01L2224/73257 , H01L2225/0651 , H01L2225/06513 , H01L2225/06541 , H01L2225/06589 , H01L2924/00014 , H01L2924/01327 , H01L2924/10253 , H01L2924/157 , H01L2924/15786 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
Abstract: A first back surface of a first chip faces toward a carrier. A first active surface of the first chip has first pads and a first insulting layer thereon. A second chip is disposed on the first chip and electrically connected to the carrier. A second active surface of the second chip faces toward the first active surface. The second active surface has second pads and a second insulting layer thereon. Bumps connect the first and second pads. First and second daisy chain circuits are respectively disposed on the first and second insulting layers. Hetero thermoelectric device pairs are disposed between the first and second chips and connected in series by the first and second daisy chain circuits, and constitute a circuit with an external device. First and second heat sinks are respectively disposed on a second surface of the carrier and a second back surface of the second chip.
Abstract translation: 第一芯片的第一后表面朝向载体。 第一芯片的第一有源表面具有第一焊盘和其上的第一绝缘层。 第二芯片设置在第一芯片上并电连接到载体。 第二芯片的第二有源表面朝向第一有源表面。 第二活性表面在其上具有第二垫和第二绝缘层。 碰撞连接第一和第二垫。 第一和第二菊花链电路分别设置在第一和第二绝缘层上。 异质热电元件对设置在第一和第二芯片之间并且由第一和第二菊花链电路串联连接，并且构成具有外部装置的电路。 第一和第二散热器分别设置在载体的第二表面和第二芯片的第二后表面上。
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公开(公告)号：US11756858B2
公开(公告)日：2023-09-12
申请号：US17140145
申请日：2021-01-04
Inventor： Wei-Kuo Han , Chia-Yen Lee , Jing-Yao Chang , Tao-Chih Chang
IPC: H01L23/40
CPC classification number: H01L23/40
Abstract: A power module including a main housing, a power element, and at least one assembling component is provided. The main housing has at least one side wall and at least two ribs extending from the side wall. The power element is disposed in the main housing and is closely pressed against a heat dissipation structure by the side wall. The assembling component includes a main section and two bending sections. The main section is located between the two ribs and includes a central portion, at least one movable component, and a peripheral portion. The central portion has a fastening portion, the peripheral portion surrounds the central portion, and the movable component is connected between the central portion and the peripheral portion. The two bending sections are respectively connected to two opposite sides of the peripheral portion and are respectively embedded in the two ribs.
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Patent Agency Ranking
公开(公告)号：US11114387B2
公开(公告)日：2021-09-07
申请号：US16108272
申请日：2018-08-22
Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
Inventor： Jing-Yao Chang , Tao-Chih Chang , Fang-Jun Leu , Wei-Kuo Han , Kuo-Shu Kao
IPC: H01L23/00
Abstract: An electronic package structure is provided. The electronic packaging structure includes a substrate, a conductive layer disposed on the substrate, an intermetallic compound disposed on the conductive layer, a stress buffering material disposed on the substrate and adjacent to the conductive layer, and an electronic device disposed on the conductive layer and the stress buffering material. The intermetallic compound is disposed between the electronic device and the conductive layer, between the electronic device and the stress buffering material, between the substrate and the stress buffering material, and between the conductive layer and the stress buffering material. A maximum thickness of the intermetallic compound disposed between the electronic device and the stress buffering material, between the substrate and the stress buffering material, and between the conductive layer and the stress buffering material is greater than the thickness of the intermetallic compound disposed between the electronic device and the conductive layer.
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公开(公告)号：US20210210409A1
公开(公告)日：2021-07-08
申请号：US17140145
申请日：2021-01-04
Inventor： Wei-Kuo Han , Chia-Yen Lee , Jing-Yao Chang , Tao-Chih Chang
IPC: H01L23/40
Abstract: A power module including a main housing, a power element, and at least one assembling component is provided. The main housing has at least one side wall and at least two ribs extending from the side wall. The power element is disposed in the main housing and is closely pressed against a heat dissipation structure by the side wall. The assembling component includes a main section and two bending sections. The main section is located between the two ribs and includes a central portion, at least one movable component, and a peripheral portion. The central portion has a fastening portion, the peripheral portion surrounds the central portion, and the movable component is connected between the central portion and the peripheral portion. The two bending sections are respectively connected to two opposite sides of the peripheral portion and are respectively embedded in the two ribs.
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公开(公告)号：US09240370B1
公开(公告)日：2016-01-19
申请号：US14569797
申请日：2014-12-15
Applicant: Industrial Technology Research Institute
Inventor： Shu-Jung Yang , Yu-Lin Chao , June-Chien Chang , Jing-Yao Chang
IPC: H01L23/495 , H01L23/522 , H01L23/00 , H01L25/07
CPC classification number: H01L25/072 , H01L23/13 , H01L23/3735 , H01L23/427 , H01L23/492 , H01L23/49811 , H01L24/29 , H01L24/32 , H01L24/33 , H01L2224/291 , H01L2224/32227 , H01L2224/32237 , H01L2224/33181 , H01L2224/83447 , H01L2924/1203 , H01L2924/13055 , H01L2924/13091 , H01L2924/15153 , H01L2924/00014 , H01L2924/014
Abstract: A power module includes a first substrate, at least two power elements, at least one conductive structure and at least one leadframe. The first substrate includes a first dielectric layer and two first metal layers. The first dielectric layer has at least two concavities and two opposite surfaces, the two first metal layers are respectively disposed on the two surfaces, and the two concavities are respectively formed on the two surfaces. The two power elements are respectively embedded in the two concavities of the first dielectric layer. The two power elements are electrically connected to each other through the conductive structure. The leadframe disposed at the first substrate is electrically connected to the two power elements, and is partially extended outside the first substrate.
Abstract translation: 功率模块包括第一衬底，至少两个功率元件，至少一个导电结构和至少一个引线框架。 第一衬底包括第一电介质层和两个第一金属层。 第一电介质层具有至少两个凹部和两个相对的表面，两个第一金属层分别设置在两个表面上，并且两个凹部分别形成在两个表面上。 两个功率元件分别嵌入在第一介电层的两个凹部中。 两个功率元件通过导电结构彼此电连接。 设置在第一基板处的引线框架电连接到两个功率元件，并且部分地延伸到第一基板的外部。
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公开(公告)号：US08866309B2
公开(公告)日：2014-10-21
申请号：US13727599
申请日：2012-12-27
Applicant: Industrial Technology Research Institute
Inventor： Jing-Yao Chang , Tao-Chih Chang , Yu-Wei Huang , Yu-Min Lin , Shin-Yi Huang
CPC classification number: H01L25/16 , H01L23/3121 , H01L23/38 , H01L24/16 , H01L24/32 , H01L24/48 , H01L24/73 , H01L25/0657 , H01L2224/16145 , H01L2224/32225 , H01L2224/48227 , H01L2224/73253 , H01L2224/73257 , H01L2225/0651 , H01L2225/06513 , H01L2225/06541 , H01L2225/06589 , H01L2924/00014 , H01L2924/01327 , H01L2924/10253 , H01L2924/157 , H01L2924/15786 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
Abstract: A first back surface of a first chip faces toward a carrier. A first active surface of the first chip has first pads and a first insulting layer thereon. A second chip is disposed on the first chip and electrically connected to the carrier. A second active surface of the second chip faces toward the first active surface. The second active surface has second pads and a second insulting layer thereon. Bumps connect the first and second pads. First and second daisy chain circuits are respectively disposed on the first and second insulting layers. Hetero thermoelectric device pairs are disposed between the first and second chips and connected in series by the first and second daisy chain circuits, and constitute a circuit with an external device. First and second heat sinks are respectively disposed on a second surface of the carrier and a second back surface of the second chip.
Abstract translation: 第一芯片的第一后表面朝向载体。 第一芯片的第一有源表面具有第一焊盘和其上的第一绝缘层。 第二芯片设置在第一芯片上并电连接到载体。 第二芯片的第二有源表面朝向第一有源表面。 第二活性表面在其上具有第二垫和第二绝缘层。 碰撞连接第一和第二垫。 第一和第二菊花链电路分别设置在第一和第二绝缘层上。 异质热电元件对设置在第一和第二芯片之间并且由第一和第二菊花链电路串联连接，并且构成具有外部装置的电路。 第一和第二散热器分别设置在载体的第二表面和第二芯片的第二后表面上。
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20.发明申请公开(公告)号：US20140097534A1
公开(公告)日：2014-04-10
申请号：US13736088
申请日：2013-01-08
Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
Inventor： Jing-Yao Chang , Tao-Chih Chang , Tung-Han Chuang , Chun-Yen Lee
IPC: H01L23/498 , H01L21/768
CPC classification number: H01L23/49811 , H01L21/76885 , H01L24/29 , H01L24/32 , H01L24/83 , H01L2224/29005 , H01L2224/29082 , H01L2224/29083 , H01L2224/29084 , H01L2224/29109 , H01L2224/29111 , H01L2224/29139 , H01L2224/29144 , H01L2224/29147 , H01L2224/29155 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/32503 , H01L2224/83065 , H01L2224/8309 , H01L2224/83091 , H01L2224/83097 , H01L2224/83191 , H01L2224/83192 , H01L2224/83193 , H01L2224/8381 , H01L2224/83825 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2924/15747 , H01L2924/00 , H01L2924/206 , H01L2924/00014
Abstract: Provided are a dual-phase intermetallic interconnection structure and a fabricating method thereof. The dual-phase intermetallic interconnection structure includes a first intermetallic compound, a second intermetallic compound, a first solder layer, and a second solder layer. The second intermetallic compound covers and surrounds the first intermetallic compound. The first intermetallic compound and the second intermetallic compound contain different high-melting point metal. The first solder layer and the second solder layer are disposed at the opposite sides of the second intermetallic compound, respectively. The first intermetallic compound is adapted to fill the micropore defects generated during the formation of the second intermetallic compound.
Abstract translation: 提供了一种双相金属间互连结构及其制造方法。 双相金属间互连结构包括第一金属间化合物，第二金属间化合物，第一焊料层和第二焊料层。 第二金属间化合物覆盖并围绕第一金属间化合物。 第一金属间化合物和第二金属间化合物含有不同的高熔点金属。 第一焊料层和第二焊料层分别设置在第二金属间化合物的相对侧。 第一金属间化合物适于填充在形成第二金属间化合物期间产生的微孔缺陷。
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