-
公开(公告)号：US20190103160A1
公开(公告)日：2019-04-04
申请号：US15721438
申请日：2017-09-29
Applicant: Intel Corporation
Inventor： Wei Fang , Prashant S. Damle , Nevil N. Gajera
IPC: G11C13/00
Abstract: In one embodiment, an apparatus comprises a first memory array comprising a plurality of phase change memory (PCM) cells; and a controller to track a first cycle count metric based at least in part on a number of writes performed to at least a portion of the first memory array; and adjust, based on the first cycle count metric, a demarcation voltage to be applied during read operations performed on PCM cells of the first memory array.
-
公开(公告)号：US09934859B1
公开(公告)日：2018-04-03
申请号：US15391763
申请日：2016-12-27
Applicant: INTEL CORPORATION
Inventor： Muthukumar P. Swaminathan , Zion S. Kwok , Prashant S. Damle , Kunal A. Khochare , Philip Hillier , Jeffrey W. Ryden , Richard P. Mangold
CPC classification number: G11C16/10 , G11C16/26 , G11C29/021 , G11C29/028
Abstract: In response to a write operation on a storage element in a non-volatile memory device, a count provided by a global counter is stored to indicate a time at which the write operation occurs on the storage element. In response to receiving a request perform a read operation on the storage element, a determination is made of a demarcation voltage to apply for performing the read operation on the storage element, based on a progress of the global counter since the write operation on the storage element.
-
公开(公告)号：US09721657B1
公开(公告)日：2017-08-01
申请号：US15089507
申请日：2016-04-02
Applicant: Intel Corporation
Inventor： Shekoufeh Qawami , Rajesh Sundaram , Prashant S. Damle , Doyle Rivers , Julie M. Walker
IPC: G11C13/00
CPC classification number: G11C13/0033 , G06F13/1668 , G11C13/0004 , G11C13/004 , G11C13/0069
Abstract: Apparatus, systems, and methods to correct for threshold voltage drift in non-volatile memory devices are disclosed and described. In one example, a compensated demarcation voltage is generated by either a time-based drift compensation scheme or a disturb-based drift compensation scheme, and read and write operations to the non-volatile memory are carried out using the compensated voltage threshold.
-
公开(公告)号：US09613691B2
公开(公告)日：2017-04-04
申请号：US14671972
申请日：2015-03-27
Applicant: Intel Corporation
Inventor： Davide Mantegazza , Prashant S. Damle , Kiran Pangal , Hanmant P. Belgal , Abhinav Pandey
CPC classification number: G11C13/004 , G11C11/5678 , G11C13/0004 , G11C13/0033 , G11C13/0069 , G11C13/0097 , G11C2013/0052 , G11C2013/0057 , G11C2013/0083
Abstract: An apparatus is provided which comprises: a plurality of memory cells; a bias logic coupled with at least one memory cell of the plurality, the bias logic to: apply a first read voltage to the at least one memory cell; and apply a second read voltage to the at least one memory cell, the first read voltage being higher than the second read voltage; and a first circuit operable to float a word-line coupled to the at least one memory cell before the bias logic applies the first read voltage to the at least one memory cell. A method is provided which comprises: performing a first read operation to at least one memory cell; and performing a second read operation to the at least one memory cell after the first read operation completes, wherein the second read operation is different from the first read operation.
-
公开(公告)号：US20220383941A1
公开(公告)日：2022-12-01
申请号：US17818553
申请日：2022-08-09
Applicant: Intel Corporation
Inventor： Rakan Maddah , Mu Lim Edwin Cheng , Bei Wang , Prashant S. Damle
IPC: G11C11/406 , G11C11/4076 , G11C11/4096
Abstract: Systems, apparatuses and methods may provide for technology that determines a power-off period associated with a non-volatile memory (NVM), sets a completion time of a write procedure corresponding to the NVM to a first value if the power-off period exceeds a threshold, and sets the completion time to a second value if the power-off period does not exceed the threshold, wherein the first value is greater than the second value.
-
Patent Agency Ranking
公开(公告)号：US10324793B2
公开(公告)日：2019-06-18
申请号：US15909929
申请日：2018-03-01
Applicant: Intel Corporation
Inventor： Kiran Pangal , Prashant S. Damle , Rajesh Sundaram , Shekoufeh Qawami , Julie M. Walker , Doyle Rivers
Abstract: Uncorrectable memory errors may be reduced by determining a logical array address for a set of memory arrays and transforming the logical array address to at least two unique array addresses based, at least in part, on logical locations of at least two memory arrays within the set of memory arrays. The at least two memory arrays are then accessed using the at least two unique array addresses, respectively.
-
公开(公告)号：US20170372780A1
公开(公告)日：2017-12-28
申请号：US15645990
申请日：2017-07-10
Applicant: Intel Corporation
Inventor： Shekoufeh Qawami , Rajesh Sundaram , Prashant S. Damle , Doyle Rivers , Julie M. Walker
IPC: G11C13/00
CPC classification number: G11C13/0033 , G06F13/1668 , G11C13/0004 , G11C13/004 , G11C13/0069
Abstract: Apparatus, systems, and methods to correct for threshold voltage drift in non-volatile memory devices are disclosed and described. In one example, a compensated demarcation voltage is generated by either a time-based drift compensation scheme or a disturb-based drift compensation scheme, and read and write operations to the non-volatile memory are carried out using the compensated voltage threshold.
-
公开(公告)号：US09824767B1
公开(公告)日：2017-11-21
申请号：US15197124
申请日：2016-06-29
Applicant: Intel Corporation
Inventor： Davide Mantegazza , Feng Pan , Prashant S. Damle , Hanmant Pramod Belgal , Kiran Pangal
CPC classification number: G11C16/3427 , G11C13/0004 , G11C13/0028 , G11C13/003 , G11C13/0033 , G11C13/004 , G11C13/0061 , G11C13/0069 , G11C16/0433 , G11C16/08 , G11C16/10 , G11C16/26 , G11C2013/0052 , G11C2013/0057 , G11C2013/0092 , G11C2213/76 , H01L27/2481 , H01L45/06
Abstract: A disclosed example to reduce a threshold voltage drift of a selector device of a memory cell includes providing an applied voltage to the selector device of the memory cell, the applied voltage being less than a threshold voltage of the selector device, and reducing the threshold voltage drift of the memory cell by maintaining the applied voltage at the selector device for a thresholding duration to activate the selector device.
-
公开(公告)号：US09792963B2
公开(公告)日：2017-10-17
申请号：US14938221
申请日：2015-11-11
Applicant: Intel Corporation
Inventor： Prashant S. Damle , Frank T. Hady , Paul D. Ruby , Kiran Pangal , Sowmiya Jayachandran
IPC: G11C11/406 , G11C7/10 , G11C16/34
CPC classification number: G11C7/1072 , G11C11/406 , G11C11/40618 , G11C16/3431
Abstract: In an embodiment, a memory controller may determine that one or more neighboring memory cells associated with a target memory cell in a memory device are to be refreshed. The controller may generate a command associated with refreshing the one or more neighboring memory cells. The controller may transfer the command from the memory controller to the memory device containing the target memory cell. The command may direct the memory device to refresh the neighboring memory cells and/or return one or more addresses associated with the neighboring memory cells.
-
公开(公告)号：US09619324B2
公开(公告)日：2017-04-11
申请号：US14126310
申请日：2013-09-27
Applicant: Intel Corporation
Inventor： Zion S. Kwok , Ravi H. Motwani , Kiran Pangal , Prashant S. Damle
CPC classification number: G06F11/1068 , G06F11/10 , G06F11/1044 , G06F11/108 , G06F12/00 , G06F2212/7207 , G11C29/52 , H03M13/1515 , H03M13/152
Abstract: Apparatus, systems, and methods for error correction in memory are described. In one embodiment, a memory controller comprises logic to receive a read request for data stored in a memory, retrieve the data and at least one associated error correction codeword, wherein the data and an associated error correction codeword is distributed across a plurality of memory devices in memory, apply a first error correction routine to decode the error correction codeword retrieved with the data and in response to an uncorrectable error in the error correction codeword, apply a second error correction routine to the plurality of devices in memory. Other embodiments are also disclosed and claimed.
-
-
-
-
-
-
-
-
-
Search Results
32
records
(took 0.014 seconds)
