公开(公告)号：US20230317847A1

公开(公告)日：2023-10-05

申请号：US17711665

申请日：2022-04-01

Applicant: Intel Corporation

Inventor： Hai Li ,  Ian Alexander Young ,  Dmitri Evgenievich Nikonov ,  Julien Sebot ,  Raseong Kim ,  Chia-Ching Lin ,  Punyashloka Debashis

IPC: H01L29/78 ,  H01L43/10

CPC classification number: H01L29/78391 ,  H01L43/10

Abstract: Technologies for majority gates are disclosed. In one embodiment, a ferroelectric layer has three inputs and an output adjacent a surface of the ferroelectric. When a voltage is applied to each input, the inputs and a ground plane below the ferroelectric layer form a capacitor. The ferroelectric layer becomes polarized based on the applied voltages at the inputs. The portion of the ferroelectric layer near the output becomes polarized in the direction of polarization of the majority of the inputs. The output voltage then reflects the majority voltage of the inputs.

公开(公告)号：US20230189659A1

公开(公告)日：2023-06-15

申请号：US17550663

申请日：2021-12-14

Applicant: Intel Corporation

Inventor： Punyashloka Debashis ,  Tanay A. Gosavi ,  Hai Li ,  Chia-Ching Lin ,  Dmitri Evgenievich Nikonov ,  Kaan Oguz ,  Ashish Verma Penumatcha ,  Marko Radosavljevic ,  Ian Alexander Young

IPC: H01L43/02 ,  H01L43/04 ,  H01L43/10 ,  H01L43/12 ,  H01L43/14

CPC classification number: H01L43/02 ,  H01L43/04 ,  H01L43/10 ,  H01L43/12 ,  H01L43/14 ,  G06F7/58

Abstract: A probabilistic bit (p-bit) comprises a magnetic tunnel junction (MTJ) comprising a free layer whose magnetization orientation randomly fluctuates in the presence of thermal noise. The p-bit MTJ comprises a reference layer, a free layer, and an insulating layer between the reference and free layers. The reference layer and the free layer comprise synthetic antiferromagnets. The use of a synthetic antiferromagnet for the reference layer reduces the amount of stray magnetic field that can impact the magnetization of the free layer and the use of a synthetic antiferromagnet for the free layer reduces stray magnetic field bias on p-bit random number generation. Tuning the thickness of the nonmagnetic layer of synthetic antiferromagnet free layer can result in faster random number generation time relative to a comparable MTJ with a free layer comprising a single-layer ferromagnet.

公开(公告)号：US20230065198A1

公开(公告)日：2023-03-02

申请号：US17465752

申请日：2021-09-02

Applicant: Intel Corporation

Inventor： Ian Alexander Young ,  Dmitri Evgenievich Nikonov ,  Chia-Ching Lin ,  Tanay A. Gosavi ,  Ashish Verma Penumatcha ,  Kaan Oguz ,  Punyashloka Debashis

IPC: H01L43/04 ,  H01L27/22 ,  H01L43/02 ,  H01L43/06 ,  H01L43/10 ,  G11C11/16 ,  G11C11/18 ,  H01F10/32

Abstract: A memory device, an integrated circuit component including an array of the memory devices, and an integrated device assembly including the integrated circuit component. The memory devices includes a first electrode; a second electrode including an antiferromagnetic (AFM) material; and a memory stack including: a first layer adjacent the second electrode and including a multilayer stack of adjacent layers comprising ferromagnetic materials; a second layer adjacent the first layer; and a third layer adjacent the second layer at one side thereof, and adjacent the first electrode at another side thereof, the second layer between the first layer and the third layer, the third layer including a ferromagnetic material. The memory device may correspond to a magnetic tunnel junction (MTJ) magnetic random access memory bit cell, and the memory stack may correspond to a MTJ device.

公开(公告)号：US20250006840A1

公开(公告)日：2025-01-02

申请号：US18344022

申请日：2023-06-29

Applicant: INTEL CORPORATION

Inventor： Rachel A. Steinhardt ,  Kevin P. O'Brien ,  Dmitri Evgenievich Nikonov ,  John J. Plombon ,  Tristan A. Tronic ,  Ian Alexander Young ,  Matthew V. Metz ,  Marko Radosavljevic ,  Carly Rogan ,  Brandon Holybee ,  Raseong Kim ,  Punyashloka Debashis ,  Dominique A. Adams ,  I-Cheng Tung ,  Arnab Sen Gupta ,  Gauri Auluck ,  Scott B. Clendenning ,  Pratyush P. Buragohain ,  Hai Li

IPC: H01L29/78 ,  H01L29/76 ,  H01L29/786

Abstract: In one embodiment, a negative capacitance transistor device includes a perovskite semiconductor material layer with first and second perovskite conductors on opposite ends of the perovskite semiconductor material layer. The device further includes a dielectric material layer on the perovskite semiconductor material layer between the first and second perovskite conductors, a perovskite ferroelectric material layer on the dielectric material layer, and a third perovskite conductor on the perovskite ferroelectric material layer.

公开(公告)号：US20250006791A1

公开(公告)日：2025-01-02

申请号：US18346227

申请日：2023-07-01

Applicant: Intel Corporation

Inventor： Rachel A. Steinhardt ,  Kevin P. O'Brien ,  Dominique A. Adams ,  Gauri Auluck ,  Pratyush P. Buragohain ,  Scott B. Clendenning ,  Punyashloka Debashis ,  Arnab Sen Gupta ,  Brandon Holybee ,  Raseong Kim ,  Matthew V. Metz ,  John J. Plombon ,  Marko Radosavljevic ,  Carly Rogan ,  Tristan A. Tronic ,  I-Cheng Tung ,  Ian Alexander Young ,  Dmitri Evgenievich Nikonov

IPC: H01L29/08 ,  H01L29/06 ,  H01L29/12 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786

Abstract: Perovskite oxide field effect transistors comprise perovskite oxide materials for the channel, source, drain, and gate oxide regions. The source and drain regions are doped with a higher concentration of n-type or p-type dopants (depending on whether the transistor is an n-type or p-type transistor) than the dopant concentration in the channel region to minimize Schottky barrier height between the source and drain regions and the source and drain metal contact and contact resistance.

公开(公告)号：US20240222506A1

公开(公告)日：2024-07-04

申请号：US18148871

申请日：2022-12-30

Applicant: Intel Corporation

Inventor： Hojoon Ryu ,  Punyashloka Debashis ,  Rachel A. Steinhardt ,  Kevin P. O'Brien ,  John J. Plombon ,  Dmitri Evgenievich Nikonov ,  Ian Alexander Young

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/8256 ,  H01L27/092 ,  H01L29/24 ,  H01L29/51 ,  H01L29/66 ,  H01L29/76

CPC classification number: H01L29/78391 ,  H01L21/02568 ,  H01L21/8256 ,  H01L27/092 ,  H01L29/24 ,  H01L29/516 ,  H01L29/66969 ,  H01L29/7606

Abstract: An apparatus, comprising a field effect transistor comprising a ferroelectric material, a channel material comprising a transition metal and a chalcogen, a source and a drain coupled to the channel material, the source and drain comprising a conductive material.

公开(公告)号：US20240206348A1

公开(公告)日：2024-06-20

申请号：US18083493

申请日：2022-12-17

Applicant: Intel Corporation

Inventor： Punyashloka Debashis ,  Ian Alexander Young ,  Dmitri Evgenievich Nikonov ,  Chia-Ching Lin ,  Hai Li

IPC: H10N52/85 ,  G11C11/16 ,  H03K19/20 ,  H10B61/00 ,  H10N50/10 ,  H10N50/85

CPC classification number: H10N52/85 ,  G11C11/161 ,  G11C11/1673 ,  G11C11/1675 ,  H03K19/20 ,  H10B61/22 ,  H10N50/10 ,  H10N50/85

Abstract: In embodiments herein, probabilistic and deterministic logic devices include reduced symmetry materials, such as two-dimensional (2D) transition metal dichalcogenide (TMD) materials (e.g., NbSe2 or MoTe2).

公开(公告)号：US20240105810A1

公开(公告)日：2024-03-28

申请号：US17952161

申请日：2022-09-23

Applicant: Intel Corporation

Inventor： Rachel A. Steinhardt ,  Ian Alexander Young ,  Dmitri Evgenievich Nikonov ,  Marko Radosavljevic ,  Matthew V. Metz ,  John J. Plombon ,  Raseong Kim ,  Kevin P. O'Brien ,  Scott B. Clendenning ,  Tristan A. Tronic ,  Dominique A. Adams ,  Carly Rogan ,  Arnab Sen Gupta ,  Brandon Holybee ,  Punyashloka Debashis ,  I-Cheng Tung ,  Gauri Auluck

IPC: H01L29/51 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/516 ,  H01L29/6684 ,  H01L29/66969 ,  H01L29/7831

Abstract: In one embodiment, transistor device includes a first source or drain material on a substrate, a semiconductor material on the first source or drain material, a second source or drain material on the semiconductor material, a dielectric layer on the substrate and adjacent the first source or drain material, a ferroelectric (FE) material on the dielectric layer and adjacent the semiconductor material, and a gate material on or adjacent to the FE material. The FE material may be a perovskite material and may have a lattice parameter that is less than a lattice parameter of the semiconductor material.

公开(公告)号：US11900979B2

公开(公告)日：2024-02-13

申请号：US17508818

申请日：2021-10-22

Applicant: INTEL CORPORATION

Inventor： Hai Li ,  Dmitri E. Nikonov ,  Punyashloka Debashis ,  Ian A. Young ,  Mahesh Subedar ,  Omesh Tickoo

IPC: G11C11/16 ,  G06F7/544 ,  G11C11/54 ,  G06N3/045 ,  G06N3/047

CPC classification number: G11C11/1673 ,  G06F7/5443 ,  G06N3/045 ,  G06N3/047 ,  G11C11/1675 ,  G11C11/1697 ,  G11C11/54

Abstract: Embodiments of the present disclosure are directed toward probabilistic in-memory computing configurations and arrangements, and configurations of probabilistic bit devices (p-bits) for probabilistic in-memory computing. concept with emerging. A probabilistic in-memory computing device includes an array of p-bits, where each p-bit is disposed at or near horizontal and vertical wires. Each p-bit is a time-varying resistor that has a time-varying resistance, which follows a desired probability distribution. The time-varying resistance of each p-bit represents a weight in a weight matrix of a stochastic neural network. During operation, an input voltage is applied to the horizontal wires to control the current through each p-bit. The currents are accumulated in the vertical wires thereby performing respective multiply-and-accumulative (MAC) operations. Other embodiments may be described and/or claimed.

公开(公告)号：US20230284457A1

公开(公告)日：2023-09-07

申请号：US17688495

申请日：2022-03-07

Applicant: Intel Corporation

Inventor： Hai Li ,  Dmitri Evgenievich Nikonov ,  Chia-Ching Lin ,  Punyashloka Debashis ,  Ian Alexander Young ,  Julien Sebot

IPC: H01L27/22 ,  H01L43/04 ,  H01L43/06

CPC classification number: H01L27/22 ,  H01L43/04 ,  H01L43/06

Abstract: In one embodiment, a first integrated circuit component, a second integrated circuit component, and an electrical interconnect coupling the first integrated circuit component and the second integrated circuit component. The interconnect comprises one or more spintronic logic devices.