公开(公告)号：US20150249131A1

公开(公告)日：2015-09-03

申请号：US14707292

申请日：2015-05-08

Applicant: Intel Corporation

Inventor： BENJAMIN CHU-KUNG ,  VAN LE ,  ROBERT CHAU ,  SANSAPTAK DASGUPTA ,  GILBERT DEWEY ,  NITIKA GOEL ,  JACK KAVALIEROS ,  MATTHEW METZ ,  NILOY MUKHERJEE ,  RAVI PILLARISETTY ,  WILLY RACHMADY ,  MARKO RADOSAVLJEVIC ,  HAN WUI THEN ,  NANCY ZELICK

IPC: H01L29/10 ,  H01L29/04 ,  H01L29/06

CPC classification number: H01L29/1033 ,  H01L21/3086 ,  H01L29/04 ,  H01L29/0665 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/165 ,  H01L29/267 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78696

Abstract: An embodiment of the invention includes an epitaxial layer that directly contacts, for example, a nanowire, fin, or pillar in a manner that allows the layer to relax with two or three degrees of freedom. The epitaxial layer may be included in a channel region of a transistor. The nanowire, fin, or pillar may be removed to provide greater access to the epitaxial layer. Doing so may allow for a “all-around gate” structure where the gate surrounds the top, bottom, and sidewalls of the epitaxial layer. Other embodiments are described herein.

Abstract translation: 本发明的实施例包括外延层，其以允许该层以两个或三个自由度放松的方式直接接触例如纳米线，翅片或支柱。 外延层可以包括在晶体管的沟道区中。 可以去除纳米线，鳍或柱以提供对外延层的更大的访问。 这样做可以允许围绕外延层的顶部，底部和侧壁的“全向栅极”结构。 本文描述了其它实施例。

公开(公告)号：US20200007135A1

公开(公告)日：2020-01-02

申请号：US16024052

申请日：2018-06-29

Applicant: INTEL CORPORATION

Inventor： ABHISHEK A. SHARMA ,  RAVI PILLARISETTY ,  CHARLES KUO ,  WILLY RACHMADY

IPC: H03M1/00 ,  H03M1/74

Abstract: Digital-to-analog converters (DACs) having a multiple-gate (multi-gate) transistor-like structure are disclosed herein. The DAC structures have a similar structure to a transistor (e.g., a MOSFET) and include source and drain regions. However, instead of employing only one gate between the source and drain regions, multiple distinct gates are employed. Each distinct gate can represent a bit for the DAC and can include different gate lengths to enable providing different current values, and thus, unique outputs. Further, N number of inputs can be applied to N number of gates employed by the DAC. The DAC structure may be configured such that the longest gate controls the LSB of the DAC and the shortest gate controls the MSB, or vice versa. In some cases, the multi-gate DAC employs high-injection velocity materials that enable compact design and routing, such as InGaAs, InP, SiGe, and Ge, to provide some examples.

公开(公告)号：US20180350880A1

公开(公告)日：2018-12-06

申请号：US15777535

申请日：2015-12-23

Applicant: INTEL CORPORATION

Inventor： PRASHANT MAJHI ,  ELIJAH V. KARPOV ,  RAVI PILLARISETTY ,  UDAY SHAH ,  NILOY MUKHERJEE

IPC: H01L27/24 ,  H01L45/00 ,  H01L43/10 ,  H01L43/02 ,  H01L27/22 ,  G11C11/16

CPC classification number: H01L27/2481 ,  G11C11/161 ,  G11C11/165 ,  G11C13/0021 ,  G11C2213/32 ,  G11C2213/71 ,  H01L27/222 ,  H01L43/02 ,  H01L43/10 ,  H01L45/08 ,  H01L45/141 ,  H01L45/146

Abstract: A non-volatile memory device is disclosed, in which a ballast resistor layer is disposed between the selector element and memory element of a given memory cell of the device. The material composition of the ballast resistor can be customized, as desired, and in some cases may be, for example, a sub-stoichiometric oxide of hafnium oxide (HfOx), tantalum oxide (TaOx), or titanium dioxide (TiOx), or an alloy of any thereof. In accordance with some embodiments, the integrated ballast resistor may serve the function of damping current surge related to the snapback characteristics of the selector element, preserving control of memory element switching. In accordance with some embodiments, an integrated ballast resistor layer provided as described herein may be implemented, for example, in any of a wide range of resistive random-access memory (RRAM) architectures and spin-transfer torque magnetic random-access memory (STTMRAM) architectures, including cross-point implementations of these types of architectures.

公开(公告)号：US20180170747A1

公开(公告)日：2018-06-21

申请号：US15576510

申请日：2015-06-26

Applicant: INTEL CORPORATION

Inventor： HAN WUI THEN ,  SANSAPTAK DASGUPTA ,  SANAZ K. GARDNER ,  RAVI PILLARISETTY ,  MARKO RADOSAVLJEVIC ,  SEUNG HOON SUNG ,  ROBERT S. CHAU

IPC: B81C1/00 ,  B81B7/02 ,  B81B3/00

CPC classification number: B81C1/00246 ,  B81B3/0021 ,  B81B7/02 ,  B81B2201/0235 ,  B81B2201/0242 ,  B81C2203/0714 ,  G01L1/18

Abstract: Techniques are disclosed for forming group III material-nitride (III-N) microelectromechanical systems (MEMS) structures on a group IV substrate, such as a silicon, silicon germanium, or germanium substrate. In some cases, the techniques include forming a III-N layer on the substrate and optionally on shallow trench isolation (STI) material, and then releasing the III-N layer by etching to form a free portion of the III-N layer suspended over the substrate. The techniques may include, for example, using a wet etch process that selectively etches the substrate and/or STI material, but does not etch the III-N material (or etches the III-N material at a substantially slower rate). Piezoresistive elements can be formed on the III-N layer to, for example, detect vibrations or deflection in the free/suspended portion of the III-N layer. Accordingly, MEMS sensors can be formed using the techniques, such as accelerometers, gyroscopes, and pressure sensors, for example.

公开(公告)号：US20170148982A1

公开(公告)日：2017-05-25

申请号：US15126138

申请日：2014-06-26

Applicant: INTEL CORPORATION

Inventor： ELIJAH V. KARPOV ,  PRASHANT MAJHI ,  RAVI PILLARISETTY ,  BRIAN S. DOYLE ,  NILOY MUKHERJEE ,  UDAY SHAH ,  ROBERT S. CHAU

IPC: H01L45/00

CPC classification number: H01L45/1206 ,  H01L29/45 ,  H01L29/4908 ,  H01L29/78618 ,  H01L29/7869 ,  H01L45/08 ,  H01L45/085 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/14 ,  H01L45/142 ,  H01L45/145 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1675

Abstract: Oxide-based three-terminal resistive switching logic devices and methods of fabricating oxide-based three-terminal resistive switching logic devices are described. In a first example, a three-terminal resistive switching logic device includes an active region disposed above a substrate. The active region includes an active oxide material region disposed directly between a metal source region and a metal drain region. The device also includes a gate electrode disposed above the active oxide material region. In a second example, a three-terminal resistive switching logic device includes an active region disposed above a substrate. The active region includes a first active oxide material region spaced apart from a second oxide material region. The device also includes metal input regions disposed on either side of the first and second active oxide material regions. A metal output region is disposed between the first and second active oxide material regions.

公开(公告)号：US20160365416A1

公开(公告)日：2016-12-15

申请号：US15120803

申请日：2014-03-28

Applicant: INTEL CORPORATION

Inventor： MATTHEW V. METZ ,  JACK T. KAVALIEROS ,  GILBERT DEWEY ,  WILLY RACHMADY ,  BENJAMIN CHU-KUNG ,  MARKO RADOSAVLJEVIC ,  HAN WUI THEN ,  RAVI PILLARISETTY ,  ROBERT S. CHAU

IPC: H01L29/205 ,  H01L29/66 ,  H01L29/78 ,  H01L21/02

CPC classification number: H01L29/205 ,  H01L21/02381 ,  H01L21/02461 ,  H01L21/02463 ,  H01L21/02466 ,  H01L21/02502 ,  H01L21/02546 ,  H01L21/02549 ,  H01L21/02639 ,  H01L21/76224 ,  H01L21/823431 ,  H01L29/1054 ,  H01L29/66522 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/785 ,  H01L29/7851

Abstract: An embodiment includes a III-V material based device, comprising: a first III-V material based buffer layer on a silicon substrate; a second III-V material based buffer layer on the first III-V material based buffer layer, the second III-V material including aluminum; and a III-V material based device channel layer on the second III-V material based buffer layer. Another embodiment includes the above subject matter and the first and second III-V material based buffer layers each have a lattice parameter equal to the III-V material based device channel layer. Other embodiments are included herein.

Abstract translation: 实施例包括基于III-V材料的器件，包括：在硅衬底上的基于第一III-V材料的缓冲层; 在第一III-V材料基缓冲层上的第二III-V材料基缓冲层，第二III-V材料包括铝; 以及在第二III-V材料基缓冲层上的基于III-V材料的器件沟道层。 另一实施例包括上述主题，第一和第二III-V材料基缓冲层各自具有等于基于III-V材料的器件沟道层的晶格参数。 本文还包括其它实施例。

公开(公告)号：US20160204246A1

公开(公告)日：2016-07-14

申请号：US14914102

申请日：2013-09-27

Applicant: INTEL CORPORATION

Inventor： RAVI PILLARISETTY ,  SANSAPTAK DASGUPTA ,  NITI GOEL ,  VAN H. LE ,  MARKO RADOSAVLJEVIC ,  GILBERT DEWEY ,  NILOY MUKHERJEE ,  MATTHEW V. METZ ,  WILLY RACHMADY ,  JACK T. KAVALIEROS ,  BENJAMIN CHU-KUNG ,  HAROLD W. KENNEL ,  STEPHEN M. CEA ,  ROBERT S. CHAU

IPC: H01L29/78 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/165 ,  H01L29/267

CPC classification number: H01L29/785 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823462 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/165 ,  H01L29/20 ,  H01L29/267 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/7851

Abstract: Ge and III-V channel semiconductor devices having maximized compliance and free surface relaxation and methods of fabricating such Ge and III-V channel semiconductor devices are described. For example, a semiconductor device includes a semiconductor fin disposed above a semiconductor substrate. The semiconductor fin has a central protruding or recessed segment spaced apart from a pair of protruding outer segments along a length of the semiconductor fin. A cladding layer region is disposed on the central protruding or recessed segment of the semiconductor fin. A gate stack is disposed on the cladding layer region. Source/drain regions are disposed in the pair of protruding outer segments of the semiconductor fin.

Abstract translation: 描述了具有最大化顺应性和自由表面弛豫的Ge和III-V沟道半导体器件以及制造这种Ge和III-V沟道半导体器件的方法。 例如，半导体器件包括设置在半导体衬底之上的半导体鳍。 半导体鳍片具有沿着半导体鳍片的长度与一对突出外部部分间隔开的中心突出或凹陷部分。 在半导体翅片的中央突出或凹陷部分上设置包覆层区域。 栅极堆叠设置在包覆层区域上。 源极/漏极区域设置在半导体鳍片的一对突出的外部段中。

公开(公告)号：US20160190319A1

公开(公告)日：2016-06-30

申请号：US14912059

申请日：2013-09-27

Applicant: INTEL CORPORATION

Inventor： JACK T. KAVALIEROS ,  MARKO RADOSAVLJEVIC ,  MATTHEW V. METZ ,  HAN WUI THEN ,  BENJAMIN CHU-KUNG ,  VAN H. LE ,  NILOY MUKHERJEE ,  SANSAPTAK DASGUPTA ,  RAVI PILLARISETTY ,  GILBERT DEWEY ,  ROBERT S. CHAU ,  NANCY M. ZELICK ,  WILLY RACHMADY

IPC: H01L29/78 ,  H01L29/165 ,  H01L29/66 ,  H01L29/267 ,  H01L29/06 ,  H01L29/161 ,  H01L29/20

CPC classification number: H01L29/7848 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/20 ,  H01L29/267 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: Non-planar semiconductor devices having multi-layered compliant substrates and methods of fabricating such non-planar semiconductor devices are described. For example, a semiconductor device includes a semiconductor fin disposed above a semiconductor substrate. The semiconductor fin has a lower portion composed of a first semiconductor material with a first lattice constant (L1), and has an upper portion composed of a second semiconductor material with a second lattice constant (L2). A cladding layer is disposed on the upper portion, but not on the lower portion, of the semiconductor fin. The cladding layer is composed of a third semiconductor material with a third lattice constant (L3), wherein L3>L2>L1. A gate stack is disposed on a channel region of the cladding layer. Source/drain regions are disposed on either side of the channel region.

Abstract translation: 描述了具有多层柔性衬底的非平面半导体器件以及制造这种非平面半导体器件的方法。 例如，半导体器件包括设置在半导体衬底之上的半导体鳍。 半导体鳍具有由具有第一晶格常数（L1）的第一半导体材料构成的下部，并且具有由具有第二晶格常数（L2）的第二半导体材料构成的上部。 在半导体翅片的上部而不是下部设置包覆层。 包覆层由具有第三晶格常数（L3）的第三半导体材料构成，其中L3> L2> L1。 栅堆叠设置在包层的沟道区上。 源极/漏极区域设置在沟道区域的两侧。

公开(公告)号：US20150097158A1

公开(公告)日：2015-04-09

申请号：US14571619

申请日：2014-12-16

Applicant: Intel Corporation

Inventor： RAVI PILLARISETTY

IPC: H01L29/417 ,  H01L21/3205 ,  H01L21/285 ,  H01L29/778 ,  H01L29/66

CPC classification number: H01L29/4175 ,  H01L21/28581 ,  H01L21/32051 ,  H01L29/1029 ,  H01L29/205 ,  H01L29/41766 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/66522 ,  H01L29/7391 ,  H01L29/772 ,  H01L29/7783

Abstract: The present disclosure relates to the fabrication of microelectronic devices having at least one negative differential resistance device formed therein. In at least one embodiment, the negative differential resistance devices may be formed utilizing quantum wells. Embodiments of negative differential resistance devices of present description may achieve high peak drive current to enable high performance and a high peak-to-valley current ratio to enable low power dissipation and noise margins, which allows for their use in logic and/or memory integrated circuitry.

Abstract translation: 本公开涉及具有形成在其中的至少一个负差分电阻器件的微电子器件的制造。 在至少一个实施例中，可以使用量子阱形成负差分电阻器件。 本描述的负差动电阻器件的实施例可实现高峰值驱动电流，以实现高性能和高峰谷电流比，以实现低功耗和噪声容限，从而使其可用于逻辑和/或存储器集成 电路。