公开(公告)号：US20200006637A1

公开(公告)日：2020-01-02

申请号：US16024714

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Tanay GOSAVI ,  Sasikanth MANIPATRUNI ,  Chia-Ching LIN ,  Kaan OGUZ ,  Christopher WIEGAND ,  Angeline SMITH ,  Noriyuki SATO ,  Kevin O'BRIEN ,  Benjamin BUFORD ,  Ian YOUNG ,  MD Tofizur RAHMAN

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/12

Abstract: Embodiments herein relate to a system, apparatus, and/or process for producing a spin orbit torque (SOT) electrode that includes a first layer with a first side to couple with a free layer of a magnetic tunnel junction (MTJ) and a second layer coupled with a second side of the first layer opposite the first side, where a value of an electrical resistance in the first SOT layer is lower than a value of an electrical resistance in the second SOT layer and where a current applied to the SOT electrode is to cause current to preferentially flow in the first SOT layer to cause a magnetic polarization of the free layer to change directions. During production of the SOT electrode, the second layer may act as an etch stop.

公开(公告)号：US20200006627A1

公开(公告)日：2020-01-02

申请号：US16022519

申请日：2018-06-28

Applicant: Intel Corporation

Inventor： Sasikanth MANIPATRUNI ,  Tanay GOSAVI ,  Ian YOUNG ,  Dmitri NIKONOV

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/10 ,  G11C11/16 ,  H01L43/12

Abstract: A memory device comprises a substrate having a front side and a backside, wherein a first conductive line is on the backside and a second conductive line is on the front side. A transistor is on the front side between the second conductive line and the substrate. A magnetic tunnel junction (MTJ) is on the backside between the first conductive line and the substrate, wherein one end of the MTJ is coupled through the substrate to the transistor and an opposite end of the MTJ is connected to the first conductive line, and wherein the transistor is further connected to the second conductive line on the front side.

公开(公告)号：US20190189173A1

公开(公告)日：2019-06-20

申请号：US16326308

申请日：2016-09-30

Applicant: INTEL CORPORATION

Inventor： Sasikanth MANIPATRUNI ,  Ian YOUNG ,  Dmitri NIKONOV

IPC: G11C11/16 ,  H03K19/16 ,  H01L29/66 ,  H01L29/82 ,  H03K19/18

CPC classification number: G11C11/161 ,  H01L29/66984 ,  H01L29/82 ,  H01L43/06 ,  H03K19/16 ,  H03K19/18

Abstract: Methods and apparatus for complex number generation and operation on a chip are disclosed. A disclosed logic device includes a first magnet with a first preferred direction of magnetization to polarize a spin of electrons in the first direction. The example logic device includes a second magnet with a second preferred direction of magnetization that polarizes a spin of electrons in the second direction. The example logic device includes a third magnet providing a free layer without a preferred direction of magnetization that is connected to the first and second magnets, wherein the third magnet encodes a vector based on a flux of electrons spin polarized in the first direction and a flux of electrons spin polarized in the second direction.

公开(公告)号：US20190013063A1

公开(公告)日：2019-01-10

申请号：US16079400

申请日：2016-03-23

Applicant: Intel Corporation

Inventor： Huichu LIU ,  Sasikanth MANIPATRUNI ,  Daniel H. MORRIS ,  Kaushik VAIDYANATHAN ,  Niloy MUKHERJEE ,  Dmitri E. NIKONOV ,  Ian YOUNG ,  Tanay KARNIK

IPC: G11C11/413 ,  G11C11/412 ,  G11C13/00 ,  G11C14/00 ,  G11C7/10

CPC classification number: G11C11/413 ,  G11C7/1045 ,  G11C7/1057 ,  G11C7/20 ,  G11C11/412 ,  G11C13/0007 ,  G11C14/009 ,  G11C2213/70 ,  G11C2213/71

Abstract: One embodiment provides an apparatus. The apparatus includes a pair of nonvolatile resistive random access memory (RRAM) memory cells coupled to a volatile static RAM (SRAM) memory cell. The pair of nonvolatile RRAM memory cells includes a first RRAM memory cell and a second RRAM memory cell. The first RRAM memory cell includes a first resistive memory element coupled to a first bit line, and a first selector transistor coupled between the first resistive memory element and a first output node of the volatile SRAM memory cell. The second RRAM memory cell includes a second resistive memory element coupled to a second bit line, and a second selector transistor coupled between the second resistive memory element and a second output node of the volatile SRAM memory cell.

公开(公告)号：US20180158587A1

公开(公告)日：2018-06-07

申请号：US15569975

申请日：2015-06-24

Applicant: Intel Corporation

Inventor： Sasikanth MANIPATRUNI ,  Anurag CHAUDHRY ,  Dmitri E. NIKONOV ,  David J. MICHALAK ,  Ian A. YOUNG

IPC: H01F10/32 ,  H01F41/30

CPC classification number: H01F10/3254 ,  B82Y25/00 ,  H01F10/1936 ,  H01F10/30 ,  H01F10/329 ,  H01F41/308 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12 ,  H03K19/16

Abstract: Described is an apparatus which comprises: an input magnet formed of one or more materials with a sufficiently high anisotropy and sufficiently low magnetic saturation to increase injection of spin currents; and a first interface layer coupled to the input magnet, wherein the first interface layer is formed of non-magnetic material such that the first interface layer and the input magnet together have sufficiently matched atomistic crystalline layers.

公开(公告)号：US20220012581A1

公开(公告)日：2022-01-13

申请号：US17484828

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Abhishek SHARMA ,  Jack T. KAVALIEROS ,  Ian A. YOUNG ,  Ram KRISHNAMURTHY ,  Sasikanth MANIPATRUNI ,  Uygar AVCI ,  Gregory K. CHEN ,  Amrita MATHURIYA ,  Raghavan KUMAR ,  Phil KNAG ,  Huseyin Ekin SUMBUL ,  Nazila HARATIPOUR ,  Van H. LE

IPC: G06N3/063 ,  H01L27/108 ,  H01L27/11502 ,  G06N3/04 ,  G06F17/16 ,  H01L27/11 ,  G11C11/54 ,  G11C7/10

Abstract: An apparatus is described. The apparatus includes a compute-in-memory (CIM) circuit for implementing a neural network disposed on a semiconductor chip. The CIM circuit includes a mathematical computation circuit coupled to a memory array. The memory array includes an embedded dynamic random access memory (eDRAM) memory array. Another apparatus is described. The apparatus includes a compute-in-memory (CIM) circuit for implementing a neural network disposed on a semiconductor chip. The CIM circuit includes a mathematical computation circuit coupled to a memory array. The mathematical computation circuit includes a switched capacitor circuit. The switched capacitor circuit includes a back-end-of-line (BEOL) capacitor coupled to a thin film transistor within the metal/dielectric layers of the semiconductor chip. Another apparatus is described. The apparatus includes a compute-in-memory (CIM) circuit for implementing a neural network disposed on a semiconductor chip. The CIM circuit includes a mathematical computation circuit coupled to a memory array. The mathematical computation circuit includes an accumulation circuit. The accumulation circuit includes a ferroelectric BEOL capacitor to store a value to be accumulated with other values stored by other ferroelectric BEOL capacitors.

公开(公告)号：US20200313075A1

公开(公告)日：2020-10-01

申请号：US16367129

申请日：2019-03-27

Applicant: Intel Corporation

Inventor： Noriyuki SATO ,  Angeline SMITH ,  Tanay GOSAVI ,  Sasikanth MANIPATRUNI ,  Kaan OGUZ ,  Kevin O'Brien ,  Benjamin BUFORD ,  Tofizur RAHMAN ,  Rohan PATIL ,  Nafees KABIR ,  Michael CHRISTENSON ,  Ian YOUNG ,  Hui Jae YOO ,  Christopher WIEGAND

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/10 ,  G11C11/16 ,  H01F10/32

Abstract: A memory device includes a first electrode including a spin-orbit material, a magnetic junction on a portion of the first electrode and a first structure including a dielectric on a portion of the first electrode. The first structure has a first sidewall and a second sidewall opposite to the first sidewall. The memory device further includes a second structure on a portion of the first electrode, where the second structure has a sidewall adjacent to the second sidewall of the first structure. The memory device further includes a first conductive interconnect above and coupled with each of the magnetic junction and the second structure and a second conductive interconnect below and coupled with the first electrode, where the second conductive interconnect is laterally distant from the magnetic junction and the second structure.

公开(公告)号：US20200227105A1

公开(公告)日：2020-07-16

申请号：US16246362

申请日：2019-01-11

Applicant: Intel Corporation

Inventor： Tanay GOSAVI ,  Sasikanth MANIPATRUNI ,  Chia-Ching LIN ,  Kaan OGUZ ,  Ian YOUNG

IPC: G11C11/16 ,  H01L43/12 ,  H01L43/10 ,  H01L43/08 ,  H01L43/02

Abstract: A memory device includes a spin orbit electrode structure having a dielectric structure including a first sidewall, a second sidewall opposite to the first sidewall, a top surface. The spin orbit electrode structure further includes an electrode having a spin orbit material adjacent to the dielectric structure, where the electrode has a first electrode portion on the top surface, a second electrode portion adjacent to the first sidewall and a third electrode portion adjacent to the second sidewall. The first electrode portion, the second electrode portion and the third electrode portion are contiguous. The spin orbit electrode structure further includes a conductive interconnect in contact with the second electrode portion or the third electrode portion. The memory device further includes a magnetic junction device on a portion of the top surface of the first electrode portion.

公开(公告)号：US20200212291A1

公开(公告)日：2020-07-02

申请号：US16236060

申请日：2018-12-28

Applicant: Intel Corporation

Inventor： Chia-Ching LIN ,  Sasikanth MANIPATRUNI ,  Tanay GOSAVI ,  Dmitri NIKONOV ,  Kaan OGUZ ,  Ian A. YOUNG

IPC: H01L43/02 ,  H01L43/10 ,  H01L43/12 ,  H01L27/22 ,  H01F10/32 ,  H01L27/11 ,  G11C11/16 ,  G11C11/14

Abstract: A memory device comprises an interconnect comprises a spin orbit coupling (SOC) material. A free magnetic layer is on the interconnect, a barrier material is over the free magnetic layer and a fixed magnetic layer is over the barrier material, wherein the free magnetic layer comprises an antiferromagnet. In another embodiment, memory device comprises a spin orbit coupling (SOC) interconnect and an antiferromagnet (AFM) free magnetic layer is on the interconnect. A ferromagnetic magnetic tunnel junction (MTJ) device is on the AFM free magnetic layer, wherein the ferromagnetic MTJ comprises a free magnet layer, a fixed magnet layer, and a barrier material between the free magnet layer and the fixed magnet layer.

公开(公告)号：US20190102170A1

公开(公告)日：2019-04-04

申请号：US16146430

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Gregory K. CHEN ,  Raghavan KUMAR ,  Huseyin Ekin SUMBUL ,  Phil KNAG ,  Ram KRISHNAMURTHY ,  Sasikanth MANIPATRUNI ,  Amrita MATHURIYA ,  Abhishek SHARMA ,  Ian A. YOUNG

IPC: G06F9/30 ,  G06F9/38 ,  G11C11/419 ,  G11C13/00

Abstract: A compute-in-memory (CIM) circuit that enables a multiply-accumulate (MAC) operation based on a current-sensing readout technique. An operational amplifier coupled with a bitline of a column of bitcells included in a memory array of the CIM circuit to cause the bitcells to act like ideal current sources for use in determining an analog voltage value outputted from the operational amplifier for given states stored in the bitcells and for given input activations for the bitcells. The analog voltage value sensed by processing circuitry of the CIM circuit and converted to a digital value to compute a multiply-accumulate (MAC) value.