公开(公告)号：US09704978B2

公开(公告)日：2017-07-11

申请号：US15074148

申请日：2016-03-18

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Alan B. Botula ,  Max L. Lifson ,  James A. Slinkman ,  Theodore G. Van Kessel ,  Randy L. Wolf

IPC: H01L29/08 ,  H01L29/732 ,  H01L23/367 ,  H01L23/373 ,  H01L29/78 ,  H01L29/45 ,  H01L23/525 ,  H01L21/02 ,  H01L21/285 ,  H01L21/762 ,  H01L49/02 ,  H01L29/06 ,  H01L29/10 ,  B82Y10/00 ,  H01L29/417 ,  H01L29/41 ,  H01L21/48 ,  H01L23/48 ,  H01L23/485

CPC classification number: H01L23/3677 ,  B82Y10/00 ,  H01L21/02112 ,  H01L21/02178 ,  H01L21/02189 ,  H01L21/02271 ,  H01L21/02488 ,  H01L21/02554 ,  H01L21/02603 ,  H01L21/02628 ,  H01L21/28518 ,  H01L21/2855 ,  H01L21/28568 ,  H01L21/2885 ,  H01L21/32051 ,  H01L21/32053 ,  H01L21/4882 ,  H01L21/7624 ,  H01L23/3731 ,  H01L23/3738 ,  H01L23/481 ,  H01L23/485 ,  H01L23/5256 ,  H01L28/20 ,  H01L29/0649 ,  H01L29/0676 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/413 ,  H01L29/41725 ,  H01L29/45 ,  H01L29/456 ,  H01L29/732 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An approach for heat dissipation in integrated circuit devices is provided. A method includes forming an isolation layer on an electrically conductive feature of an integrated circuit device. The method also includes forming an electrically conductive layer on the isolation layer. The method additionally includes forming a plurality of nanowire structures on a surface of the electrically conductive layer.

公开(公告)号：US09530711B2

公开(公告)日：2016-12-27

申请号：US14715693

申请日：2015-05-19

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Alan B. Botula ,  Alvin J. Joseph ,  James A. Slinkman ,  Randy L. Wolf

IPC: H01L29/76 ,  H01L29/66 ,  H01L27/12 ,  H01L21/84 ,  H01L23/24 ,  H01L23/34 ,  H01L29/78 ,  H01L23/367

CPC classification number: H01L23/34 ,  H01L21/84 ,  H01L23/3677 ,  H01L27/1203 ,  H01L29/665 ,  H01L29/78 ,  H01L29/7841 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An approach for sinking heat from a transistor is provided. A method includes forming a substrate contact extending from a first portion of a silicon-on-insulator (SOI) island to a substrate. The method also includes forming a transistor in a second portion of the SOI island. The method further includes electrically isolating the substrate contact from the transistor by doping the first portion of the SOI island.

公开(公告)号：US09324628B2

公开(公告)日：2016-04-26

申请号：US14189284

申请日：2014-02-25

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Alan B. Botula ,  Max L. Lifson ,  James A. Slinkman ,  Theodore G. Van Kessel ,  Randy L. Wolf

IPC: H01L29/08 ,  H01L23/373 ,  H01L29/78 ,  H01L29/45 ,  H01L23/525 ,  H01L21/02 ,  H01L21/285 ,  H01L23/367 ,  B82Y10/00 ,  H01L29/417 ,  H01L29/06 ,  H01L29/41

CPC classification number: H01L23/3677 ,  B82Y10/00 ,  H01L21/02112 ,  H01L21/02178 ,  H01L21/02189 ,  H01L21/02271 ,  H01L21/02488 ,  H01L21/02554 ,  H01L21/02603 ,  H01L21/02628 ,  H01L21/28518 ,  H01L21/2855 ,  H01L21/28568 ,  H01L21/2885 ,  H01L21/32051 ,  H01L21/32053 ,  H01L21/4882 ,  H01L21/7624 ,  H01L23/3731 ,  H01L23/3738 ,  H01L23/481 ,  H01L23/485 ,  H01L23/5256 ,  H01L28/20 ,  H01L29/0649 ,  H01L29/0676 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/413 ,  H01L29/41725 ,  H01L29/45 ,  H01L29/456 ,  H01L29/732 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An approach for heat dissipation in integrated circuit devices is provided. A method includes forming an isolation layer on an electrically conductive feature of an integrated circuit device. The method also includes forming an electrically conductive layer on the isolation layer. The method additionally includes forming a plurality of nanowire structures on a surface of the electrically conductive layer.

Abstract translation: 提供集成电路器件散热方法。 一种方法包括在集成电路器件的导电特征上形成隔离层。 该方法还包括在隔离层上形成导电层。 该方法还包括在导电层的表面上形成多个纳米线结构。

公开(公告)号：US20140004687A1

公开(公告)日：2014-01-02

申请号：US14018814

申请日：2013-09-05

Applicant: International Business Machines Corporation

Inventor： Alan B. Botula ,  John J. Ellis-Monaghan ,  Alvin J. Joseph ,  Max G. Levy ,  Richard A. Phelps ,  James A. Slinkman ,  Randy L. Wolf

IPC: H01L21/02

CPC classification number: H01L21/02488 ,  H01L21/2652 ,  H01L21/7624 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/78603

Abstract: Disclosed is semiconductor structure with an insulator layer on a semiconductor substrate and a device layer is on the insulator layer. The substrate is doped with a relatively low dose of a dopant having a given conductivity type such that it has a relatively high resistivity. Additionally, a portion of the semiconductor substrate immediately adjacent to the insulator layer can be doped with a slightly higher dose of the same dopant, a different dopant having the same conductivity type or a combination thereof. Optionally, micro-cavities are created within this same portion so as to balance out any increase in conductivity due to increased doping with a corresponding increase in resistivity. Increasing the dopant concentration at the semiconductor substrate-insulator layer interface raises the threshold voltage (Vt) of any resulting parasitic capacitors and, thereby reduces harmonic behavior. Also disclosed herein are embodiments of a method for forming such a semiconductor structure.

Abstract translation: 公开了在半导体衬底上具有绝缘体层并且器件层位于绝缘体层上的半导体结构。 衬底掺杂有相对低剂量的具有给定导电类型的掺杂剂，使得其具有相对高的电阻率。 此外，与绝缘体层紧密相邻的半导体衬底的一部分可掺杂略高的相同掺杂剂剂量，具有相同导电类型的不同掺杂剂或其组合。 可选地，在该相同部分内形成微腔，以便平衡由于掺杂增加导致的电导率的增加，同时具有相应的电阻率增加。 增加半导体衬底 - 绝缘体层界面处的掺杂剂浓度会提高任何结果的寄生电容器的阈值电压（Vt），从而降低谐波行为。 本文还公开了用于形成这种半导体结构的方法的实施例。

公开(公告)号：US11152495B2

公开(公告)日：2021-10-19

申请号：US16587290

申请日：2019-09-30

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Alan B. Botula ,  Max L. Lifson ,  James A. Slinkman ,  Theodore G. Van Kessel ,  Randy L. Wolf

IPC: H01L29/732 ,  H01L23/373 ,  H01L29/78 ,  H01L29/45 ,  H01L23/525 ,  H01L21/02 ,  H01L21/285 ,  H01L29/10 ,  H01L29/08 ,  H01L49/02 ,  H01L29/06 ,  H01L21/762 ,  B82Y10/00 ,  H01L29/417 ,  H01L29/41 ,  H01L23/367 ,  H01L21/48 ,  H01L21/288 ,  H01L21/3205 ,  H01L23/48 ,  H01L23/485 ,  H01L29/66

Abstract: An approach for heat dissipation in integrated circuit devices is provided. A method includes forming an isolation layer on an electrically conductive feature of an integrated circuit device. The method also includes forming an electrically conductive layer on the isolation layer. The method additionally includes forming a plurality of nanowire structures on a surface of the electrically conductive layer.

公开(公告)号：US09472570B2

公开(公告)日：2016-10-18

申请号：US14182459

申请日：2014-02-18

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Alan B. Botula ,  Randy L. Wolf

IPC: H01L27/12 ,  H01L27/06 ,  H01L29/66 ,  H01L21/768 ,  H01L21/84 ,  H01L23/528 ,  H01L27/07 ,  H01L29/861 ,  H01L29/423

CPC classification number: H01L27/1203 ,  H01L21/768 ,  H01L21/84 ,  H01L23/528 ,  H01L27/0629 ,  H01L27/0727 ,  H01L29/42372 ,  H01L29/66136 ,  H01L29/66568 ,  H01L29/78615 ,  H01L29/861 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Approaches for body contacted transistors are provided. A method of manufacturing a semiconductor structure includes forming a field effect transistor (FET) including a channel and a gate. The method also includes forming a diode that is electrically connected between the channel and the gate, wherein the diode and channel are contained in a same layer of material.

Abstract translation: 提供了体接触晶体管的方法。 制造半导体结构的方法包括形成包括沟道和栅极的场效应晶体管（FET）。 该方法还包括形成电连接在沟道和栅极之间的二极管，其中二极管和沟道被包含在相同的材料层中。

公开(公告)号：US20150072504A1

公开(公告)日：2015-03-12

申请号：US14546058

申请日：2014-11-18

Applicant: International Business Machines Corporation

Inventor： Alan B. Botula ,  Jeffrey E. Hanrahan ,  Mark D. Jaffe ,  Alvin J. Joseph ,  Dale W. Martin ,  Gerd Pfeiffer ,  James A. Slinkman

IPC: H01L21/762 ,  H01L21/324 ,  H01L21/265

CPC classification number: H01L21/76251 ,  H01L21/04 ,  H01L21/265 ,  H01L21/26506 ,  H01L21/324

Abstract: According to a method herein, a first side of a substrate is implanted with a first material to change a crystalline structure of the first side of the substrate from a first crystalline state to a second crystalline state, after the first material is implanted. A second material is deposited on the first side of the substrate, after the first material is implanted. A first side of an insulator layer is bonded to the second material on the first side of the substrate. Integrated circuit devices are formed on a second side of the insulator layer, opposite the first side of the insulator layer, after the insulator layer is bonded to the second material. The integrated circuit devices are thermally annealed. The first material maintains the second crystalline state of the first side of the substrate during the annealing.

Abstract translation: 根据本文的方法，在第一材料被植入之后，衬底的第一侧被注入第一材料，以将衬底的第一侧的结晶结构从第一结晶状态改变到第二结晶状态。 在植入第一种材料之后，第二种材料沉积在基底的第一面上。 绝缘体层的第一面在衬底的第一侧上与第二材料接合。 在绝缘体层与第二材料结合之后，在绝缘体层的与绝缘体层的第一侧相对的第二侧上形成集成电路器件。 集成电路器件进行热退火。 第一种材料在退火过程中保持衬底的第一面的第二结晶状态。

公开(公告)号：US08912597B2

公开(公告)日：2014-12-16

申请号：US13946362

申请日：2013-07-19

Applicant: International Business Machines Corporation

Inventor： Alan B. Botula ,  Robert M. Rassel ,  Yun Shi ,  Mark E. Stidham

IPC: H01L29/78 ,  H01L21/265 ,  H01L29/66

CPC classification number: H01L29/7833 ,  H01L21/26586 ,  H01L29/66659 ,  H01L29/7835

Abstract: A semiconductor device is disclosed. The semiconductor device includes a semiconductor substrate including a first source drain region, a second source drain region, and an intrinsic region therebetween; an asymmetric lightly doped drain (LDD) region within the substrate, wherein the asymmetric LDD region extends from the first source drain region into the intrinsic region between the first source drain region and the second source drain region; and a gate positioned atop the semiconductor substrate, wherein an outer edge of the gate overlaps the second source drain region. A related method and design structure are also disclosed.

Abstract translation: 公开了一种半导体器件。 半导体器件包括：半导体衬底，包括第一源极漏极区域，第二源极漏极区域及其之间的固有区域; 在所述衬底内的不对称轻掺杂漏极（LDD）区域，其中所述不对称LDD区域从所述第一源极漏极区域延伸到所述第一源极漏极区域和所述第二源极漏极区域之间的本征区域; 以及位于所述半导体衬底顶部的栅极，其中所述栅极的外边缘与所述第二源极漏极区重叠。 还公开了相关的方法和设计结构。

公开(公告)号：US20140213036A1

公开(公告)日：2014-07-31

申请号：US14230206

申请日：2014-03-31

Applicant: International Business Machines Corporation

Inventor： Alan B. Botula ,  Renata Camillo-Castillo ,  James S. Dunn ,  Jeffrey P. Gambino ,  Douglas B. Hershberger ,  Alvin J. Joseph ,  Robert M. Rassel ,  Mark E. Stidham

IPC: H01L21/762

CPC classification number: H01L21/76224 ,  H01L21/26506 ,  H01L21/823892 ,  H01L27/04 ,  H01L27/0623 ,  H01L27/0635 ,  H01L27/0802 ,  H01L27/0811 ,  H01L27/0928

Abstract: A substrate includes a first region having a first resistivity, for optimizing a field effect transistor, a second region having a second resistivity, for optimizing an npn subcollector of a bipolar transistor device and triple well, a third region having a third resistivity, with a high resistivity for a passive device, a fourth region, substantially without implantation, to provide low perimeter capacitance for devices.

Abstract translation: 衬底包括具有第一电阻率的第一区域，用于优化场效应晶体管，具有第二电阻率的第二区域，用于优化双极晶体管器件和三阱的npn子集电极，具有第三电阻率的第三区域，具有第三电阻率 用于无源器件的高电阻率，第四区域，基本上没有植入，以为器件提供低周边电容。

公开(公告)号：US20140131800A1

公开(公告)日：2014-05-15

申请号：US13676817

申请日：2012-11-14

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Alan B. Botula ,  Mark D. Jaffe ,  Alvin J. Joseph ,  Richard A. Phelps ,  James Slinkman ,  Randy L. Wolf

IPC: H01L21/66 ,  H01L29/16

CPC classification number: H01L29/0603 ,  H01L21/26513 ,  H01L21/7624 ,  H01L21/84 ,  H01L22/14 ,  H01L22/20 ,  H01L27/1203 ,  H01L29/16 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A silicon device includes an active silicon layer, a buried oxide (BOX) layer beneath the active silicon layer and a high-resistivity silicon layer beneath the BOX layer. The device also includes a harmonic suppression layer at a boundary of the BOX layer and the high-resistivity silicon layer.