公开(公告)号：US20150221766A1

公开(公告)日：2015-08-06

申请号：US14679613

申请日：2015-04-06

Applicant: Infineon Technologies AG

Inventor： Hans-Joachim Schulze ,  Peter Irsigler

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/16

CPC classification number: H01L29/7813 ,  H01L21/223 ,  H01L21/26506 ,  H01L21/30604 ,  H01L21/3221 ,  H01L29/0688 ,  H01L29/0878 ,  H01L29/105 ,  H01L29/1083 ,  H01L29/16 ,  H01L29/167 ,  H01L29/36 ,  H01L29/407 ,  H01L29/66348 ,  H01L29/66734 ,  H01L29/7397 ,  Y10S438/974

Abstract: A semiconductor device includes a silicon semiconductor body having a main surface and a nitrogen concentration which is lower than about 2*1014 cm−3 at least in a first portion of the silicon semiconductor body, the first portion extending from the main surface to a depth of about 50 μm. The nitrogen concentration increases with a distance from the main surface at least in the first portion. The semiconductor device further includes a field-effect structure arranged next to the main surface.

Abstract translation: 半导体器件至少在硅半导体本体的第一部分中包括具有主表面和氮浓度低于约2×10 14 cm -3的硅半导体本体，第一部分从主表面延伸到深度 约50μm。 氮浓度至少在第一部分与主表面的距离增加。 半导体器件还包括邻近主表面布置的场效应结构。

公开(公告)号：US20150137224A1

公开(公告)日：2015-05-21

申请号：US14082491

申请日：2013-11-18

Applicant: Infineon Technologies AG

Inventor： Andreas Meiser ,  Rolf Weis ,  Franz Hirler ,  Martin Vielemeyer ,  Markus Zundel ,  Peter Irsigler

IPC: H01L29/78 ,  H01L27/12 ,  H01L29/66 ,  H01L29/10 ,  H01L29/40 ,  H01L29/417

CPC classification number: H01L29/4175 ,  H01L27/1203 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/66696 ,  H01L29/7824 ,  H01L29/7825 ,  H01L29/7826 ,  H01L29/7835

Abstract: A semiconductor device comprises a transistor formed in a semiconductor body having a first main surface. The transistor comprises a source region, a drain region, a channel region, a drift zone, a source contact electrically connected to the source region, a drain contact electrically connected to the drain region, and a gate electrode at the channel region. The channel region and the drift zone are disposed along a first direction between the source region and the drain region, the first direction being parallel to the first main surface. The channel region has a shape of a first ridge extending along the first direction. One of the source contact and the drain contact is adjacent to the first main surface, the other one of the source contact and the drain contact is adjacent to a second main surface that is opposite to the first main surface.

Abstract translation: 半导体器件包括形成在具有第一主表面的半导体本体中的晶体管。 晶体管包括源极区，漏极区，沟道区，漂移区，电连接到源极区的源极接触，电连接到漏极区的漏极接触，以及沟道区处的栅电极。 沟道区域和漂移区域沿着源极区域和漏极区域之间的第一方向设置，第一方向平行于第一主表面。 通道区域具有沿着第一方向延伸的第一脊的形状。 源极接触和漏极接触中的一个与第一主表面相邻，源极接触和漏极接触中的另一个与与第一主表面相对的第二主表面相邻。

公开(公告)号：US08956960B2

公开(公告)日：2015-02-17

申请号：US13679347

申请日：2012-11-16

Applicant: Infineon Technologies AG

Inventor： Peter Irsigler ,  Hans-Joachim Schulze

IPC: H01L21/20 ,  H01L21/36 ,  H01L21/762 ,  C30B25/18 ,  C30B25/04

CPC classification number: H01L21/76224 ,  C30B25/04 ,  C30B25/183 ,  C30B29/403 ,  C30B29/406 ,  C30B29/42 ,  C30B29/44 ,  H01L25/167 ,  H01L27/153 ,  H01L33/007 ,  H01L33/0079 ,  H01L33/12 ,  H01L2924/0002 ,  H01L2924/00

Abstract: According to an embodiment, a method for stress-reduced forming a semiconductor device includes: providing a semiconductor wafer including an upper side and a first semiconductor layer of a first semiconductor material at the upper side; forming, in a vertical cross-section which is substantially orthogonal to the upper side, at the upper side a plurality of first vertical trenches and a plurality of second vertical trenches between adjacent first vertical trenches so that the first vertical trenches have, in the vertical cross-section, a larger horizontal extension than the second vertical trenches; and forming a plurality of third semiconductor layers at the upper side which are, in the vertical cross-section, spaced apart from each other by gaps each of which overlaps, in the vertical cross-section, with a respective first vertical trench when seen from above. At least one of the third semiconductor layers includes a semiconductor material which is different to the first semiconductor material.

Abstract translation: 根据一个实施例，一种用于应力减小形成半导体器件的方法包括：在上侧提供包括第一半导体材料的上侧和第一半导体层的半导体晶片; 在与上侧基本上正交的垂直横截面中，在上侧形成有多个第一垂直沟槽和相邻的第一垂直沟槽之间的多个第二垂直沟槽，使得第一垂直沟槽在垂直方向上具有 横截面，比第二垂直沟槽更大的水平延伸; 并且在上侧形成多个第三半导体层，所述多个第三半导体层在垂直截面中彼此间隔开，每个间隙在垂直横截面中与相应的第一垂直沟槽重叠，当从 以上。 第三半导体层中的至少一个包括与第一半导体材料不同的半导体材料。

公开(公告)号：US10670972B2

公开(公告)日：2020-06-02

申请号：US14304665

申请日：2014-06-13

Applicant: Infineon Technologies AG

Inventor： Rudolf Zelsacher ,  Peter Irsigler

IPC: G03B27/32 ,  G03F7/20

Abstract: A method for exposing a structure on a substrate includes positioning of an invariable reticle and a programmable reticle in a light path between a light source and a layer on a substrate to be exposed to light and exposing the layer on the substrate by light from the light source passing the invariable reticle and the programmable reticle.

公开(公告)号：US10566426B2

公开(公告)日：2020-02-18

申请号：US15848707

申请日：2017-12-20

Applicant: Infineon Technologies AG

Inventor： Anton Mauder ,  Oliver Hellmund ,  Peter Irsigler ,  Jens Peter Konrath ,  David Laforet ,  Maik Langner ,  Markus Neuber ,  Hans-Joachim Schulze ,  Ralf Siemieniec ,  Knut Stahrenberg ,  Olaf Storbeck

IPC: H01L21/02 ,  H01L29/16 ,  H01L21/28 ,  H01L29/51

Abstract: A body structure and a drift zone are formed in a semiconductor layer, wherein the body structure and the drift zone form a first pn junction. A silicon nitride layer is formed on the semiconductor layer. A silicon oxide layer is formed from at least a vertical section of the silicon nitride layer by oxygen radical oxidation.

公开(公告)号：US10553675B2

公开(公告)日：2020-02-04

申请号：US15785627

申请日：2017-10-17

Applicant: Infineon Technologies AG

Inventor： Sebastian Schmidt ,  Donald Dibra ,  Oliver Hellmund ,  Peter Irsigler ,  Andreas Meiser ,  Hans-Joachim Schulze ,  Martina Seider-Schmidt ,  Robert Wiesner

IPC: H01L29/06 ,  H01L21/02 ,  H01L21/265 ,  H01L21/762 ,  H01L21/84 ,  H01L27/12

Abstract: In accordance with an embodiment of an integrated circuit, a cavity is buried in a semiconductor body below a first surface of the semiconductor body. An active area portion of the semiconductor body is arranged between the first surface and the cavity. The integrated circuit further includes a trench isolation structure configured to provide a lateral electric isolation of the active area portion.

公开(公告)号：US10439030B2

公开(公告)日：2019-10-08

申请号：US15646152

申请日：2017-07-11

Applicant: Infineon Technologies AG

Inventor： Andreas Meiser ,  Rolf Weis ,  Franz Hirler ,  Martin Vielemeyer ,  Markus Zundel ,  Peter Irsigler

IPC: H01L29/92 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/40 ,  H01L29/10 ,  H01L27/12 ,  H01L29/06

Abstract: A semiconductor device includes a transistor in a semiconductor body having a first main surface. The transistor includes: a source contact electrically connected to a source region; a drain contact electrically connected to a drain region; a gate electrode at the channel region, the channel region and a drift zone disposed along a first direction between the source and drain regions, the first direction being parallel to the first main surface, the channel region patterned into a ridge by adjacent gate trenches formed in the first main surface, the adjacent gate trenches spaced apart in a second direction perpendicular to the first direction, a longitudinal axis of the ridge extending in the first direction and a longitudinal axis of the gate trenches extending in the first direction; and at least one of the source and drain contacts being adjacent to a second main surface opposite the first main surface.

公开(公告)号：US10247671B2

公开(公告)日：2019-04-02

申请号：US15904463

申请日：2018-02-26

Applicant: Infineon Technologies AG

Inventor： Jonathan Silvano de Sousa ,  Thomas Grille ,  Ursula Hedenig ,  Thomas Neidhart ,  Peter Irsigler ,  Vijaye Kumar Rajaraman

IPC: G01N21/59 ,  G01N21/3504 ,  G01K11/00 ,  G02B6/125 ,  G01L7/08 ,  G02B6/12

Abstract: A sensor and methods of making a sensor are disclosed. The sensor may include a substrate including an opening, an optical source disposed in the substrate and configured to generate an optical source signal, an optical detector disposed in the substrate so that the opening is disposed between the optical source and the optical detector, a plurality of optical cavity structures disposed in the opening wherein each of the plurality of optical cavity structures contains an enclosed cavity so that the respective enclosed cavities are not in gas communication with each other, wherein the plurality of optical cavity structures are arranged in an optical path between the optical source and the optical detector, and a processing circuit coupled to the optical detector and configured to process an optical signal received by the optical detector.

公开(公告)号：US20170323858A1

公开(公告)日：2017-11-09

申请号：US15587184

申请日：2017-05-04

Applicant: Infineon Technologies AG

Inventor： Oliver Hellmund ,  Peter Irsigler ,  Sebastian Schmidt ,  Hans-Joachim Schulze ,  Martina Seider-Schmidt

IPC: H01L23/00 ,  H01L29/66 ,  H01L29/08 ,  H01L21/306 ,  H01L21/768 ,  H01L29/78 ,  H01L23/528 ,  H01L21/304

CPC classification number: H01L23/562 ,  H01L21/304 ,  H01L21/30604 ,  H01L21/30625 ,  H01L21/76895 ,  H01L23/528 ,  H01L29/0657 ,  H01L29/0865 ,  H01L29/41741 ,  H01L29/66674 ,  H01L29/66734 ,  H01L29/7801 ,  H01L29/7813

Abstract: A semiconductor device includes a power transistor in a semiconductor substrate portion, where the semiconductor substrate portion includes a central portion and a kerf, components of the power transistor are arranged in the central portion, and the central portion has a thickness d. The semiconductor device also includes a support element disposed over a main surface of the central portion, where the support element has a smallest lateral extension t at a side adjacent to the main surface of the semiconductor substrate portion and a height h, where 0.1×h≦d≦4×h and 0.1×h≦t≦1.5×h.

公开(公告)号：US20170317176A1

公开(公告)日：2017-11-02

申请号：US15646152

申请日：2017-07-11

Applicant: Infineon Technologies AG

Inventor： Andreas Meiser ,  Rolf Weis ,  Franz Hirler ,  Martin Vielemeyer ,  Markus Zundel ,  Peter Irsigler

IPC: H01L29/417 ,  H01L29/78 ,  H01L29/423 ,  H01L29/66 ,  H01L29/06 ,  H01L29/10 ,  H01L29/40 ,  H01L27/12

CPC classification number: H01L29/4175 ,  H01L27/1203 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/66696 ,  H01L29/7824 ,  H01L29/7825 ,  H01L29/7826 ,  H01L29/7835

Abstract: A semiconductor device includes a transistor in a semiconductor body having a first main surface. The transistor includes: a source contact electrically connected to a source region; a drain contact electrically connected to a drain region; a gate electrode at the channel region, the channel region and a drift zone disposed along a first direction between the source and drain regions, the first direction being parallel to the first main surface, the channel region patterned into a ridge by adjacent gate trenches formed in the first main surface, the adjacent gate trenches spaced apart in a second direction perpendicular to the first direction, a longitudinal axis of the ridge extending in the first direction and a longitudinal axis of the gate trenches extending in the first direction; and at least one of the source and drain contacts being adjacent to a second main surface opposite the first main surface.