公开(公告)号：US20190027537A1

公开(公告)日：2019-01-24

申请号：US16069165

申请日：2016-03-28

Applicant: Intel Corporation

Inventor： Christopher J. WIEGAND ,  Oleg GOLONZKA ,  MD Tofizur RAHMAN ,  Brian S. DOYLE ,  Mark L. DOCZY ,  Kevin P. O'BRIEN ,  Kaan OGUZ ,  Tahir GHANI ,  Satyarth SURI

IPC: H01L27/22 ,  H01F10/32 ,  G11C11/16 ,  H01L23/528 ,  H01L43/02 ,  H01L23/532 ,  H01L43/12 ,  H01L21/768 ,  H01F41/32

CPC classification number: H01L27/228 ,  G11C11/161 ,  H01F10/3254 ,  H01F10/329 ,  H01F41/32 ,  H01L21/0273 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/3212 ,  H01L21/32134 ,  H01L21/76802 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/7685 ,  H01L21/76877 ,  H01L23/528 ,  H01L23/53238 ,  H01L27/226 ,  H01L43/02 ,  H01L43/10 ,  H01L43/12

Abstract: Approaches for an interconnect cladding process for integrating magnetic random access memory (MRAM) devices, and the resulting structures, are described. In an example, a memory structure includes an interconnect disposed in a trench of dielectric layer above a substrates, the interconnect including a diffusion barrier layer disposed at a bottom of and along sidewalls of the trench to an uppermost surface of the dielectric layer, a conductive fill layer disposed on the diffusion barrier layer and recessed below the uppermost surface of the dielectric layer and an uppermost surface of the diffusion barrier layer, and a conductive capping layer disposed on the conductive fill layer and between sidewall portions of the diffusion barrier layer. A memory element is disposed on the conductive capping layer of the interconnect.

公开(公告)号：US20180248116A1

公开(公告)日：2018-08-30

申请号：US15753468

申请日：2015-09-18

Applicant: Intel Corporation

Inventor： Mark L. DOCZY ,  Brian S. DOYLE ,  Charles C. KUO ,  Kaan OGUZ ,  Kevin P. O'BRIEN ,  Satyarth SURI ,  Tejaswi K. INDUKURI

IPC: H01L43/12 ,  H01F10/32 ,  H01L43/08 ,  G11C11/16 ,  H01F41/34 ,  H01L27/22 ,  H01L43/02 ,  H01L43/10

CPC classification number: H01L43/12 ,  G11C11/161 ,  H01F10/3254 ,  H01F10/3272 ,  H01F10/3286 ,  H01F10/329 ,  H01F41/34 ,  H01L27/222 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10

Abstract: Technologies for manufacturing spin transfer torque memory (STTM) elements are disclosed. In some embodiments, the technologies include methods for removing a re-deposited layer and/or interrupting the electrical continuity of a re-deposited layer that may form on one or more sidewalls of an STTM element during its formation. Devices and systems including such STTM elements are also described.

公开(公告)号：US20170345476A1

公开(公告)日：2017-11-30

申请号：US15503359

申请日：2014-09-26

Applicant: Intel Corporation

Inventor： Mark L. DOCZY ,  Kaan OGUZ ,  Brian S. DOYLE ,  Charles C. KUO ,  Robert S. CHAU ,  Satyarth SURI

IPC: G11C11/16 ,  H01L43/10 ,  H01L27/22 ,  H01L43/12 ,  H01F10/32

CPC classification number: G11C11/161 ,  H01F10/3286 ,  H01L27/222 ,  H01L43/10 ,  H01L43/12

Abstract: A material layer stack for a magnetic tunneling junction, the material layer stack including a fixed magnetic layer; a dielectric layer; a free magnetic layer; and an amorphous electrically-conductive seed layer, wherein the fixed magnetic layer is disposed between the dielectric layer and the seed layer. A non-volatile memory device including a material stack including an amorphous electrically-conductive seed layer; and a fixed magnetic layer juxtaposed and in contact with the seed layer. A method including forming an amorphous seed layer on a first electrode of a memory device; forming a material layer stack on the amorphous seed layer, the material stack including a dielectric layer disposed between a fixed magnetic layer and a free magnetic layer, wherein the fixed magnetic layer.

公开(公告)号：US20170271578A1

公开(公告)日：2017-09-21

申请号：US15503357

申请日：2014-09-26

Applicant: Intel Corporation

Inventor： Kevin P. O'BRIEN ,  Brian S. DOYLE ,  Kaan OGUZ ,  Robert S. CHAU ,  Satyarth SURI

IPC: H01L43/12 ,  H01L43/08 ,  H01L43/10 ,  G11C11/16

CPC classification number: H01L43/12 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1675 ,  H01L43/08 ,  H01L43/10

Abstract: A method including forming a device stack including a dielectric layer between a fixed magnetic layer and a free magnetic layer on a fully-crystalline sacrificial film or substrate including a crystal lattice similar to the crystal lattice of the dielectric material; and transferring the device stack from the sacrificial film to a device substrate. An apparatus including a device stack including a dielectric layer between a fixed magnetic layer and a free magnetic layer on a device substrate wherein the fixed magnetic layer and the free magnetic layer each have a crystalline lattice conforming to a crystalline lattice of the sacrificial film or substrate on which they were formed prior to transfer to the device substrate.

公开(公告)号：US20230411278A1

公开(公告)日：2023-12-21

申请号：US18129264

申请日：2023-03-31

Applicant: Intel Corporation

Inventor： Chia-Ching LIN ,  Sou-Chi CHANG ,  Kaan OGUZ ,  Arnab SEN GUPTA ,  I-Cheng TUNG ,  Matthew V. METZ ,  Sudarat LEE ,  Scott B. CLENDENNING ,  Uygar E. AVCI ,  Aaron J. WELSH

IPC: H01L23/522 ,  H01L27/08

CPC classification number: H01L23/5223 ,  H01L28/75 ,  H01L28/91 ,  H01L27/0805

Abstract: Metal insulator metal capacitors are described. In an example, a metal-insulator-metal (MIM) capacitor includes a first electrode that includes a bottom region and a pair of vertical regions. First metal layers are outside the vertical regions and in contact with the vertical regions. An insulator is over the first electrode. A second electrode is over the insulator. A second metal layer is on a top surface of the second electrode.

公开(公告)号：US20230102177A1

公开(公告)日：2023-03-30

申请号：US17484981

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Chia-Ching LIN ,  Sou-Chi CHANG ,  Kaan OGUZ ,  I-Cheng TUNG ,  Arnab SEN GUPTA ,  Ian A. YOUNG ,  Uygar E. AVCI ,  Matthew V. METZ

IPC: H01G4/08 ,  H01L49/02 ,  H01G4/30

Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques related to stacked MIM capacitors with multiple metal and dielectric layers that include insulating spacers on edges of one or more of the multiple layers to prevent unintended electrical coupling between metal layers during manufacturing. The dielectric layers may include Perovskite-based materials. Other embodiments may be described and/or claimed.

公开(公告)号：US20230100952A1

公开(公告)日：2023-03-30

申请号：US17485291

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： I-Cheng TUNG ,  Ashish Verma PENUMATCHA ,  Seung Hoon SUNG ,  Sarah ATANASOV ,  Jack T. KAVALIEROS ,  Matther V. METZ ,  Uygar E. AVCI ,  Rahul RAMAMURTHY ,  Chia-Ching LIN ,  Kaan OGUZ

IPC: H01L29/49 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786 ,  H01L21/02 ,  H01L21/28 ,  H01L29/66

Abstract: Embodiments disclosed herein include transistors and transistor gate stacks. In an embodiment, a transistor gate stack comprises a semiconductor channel. In an embodiment, an interlayer (IL) is over the semiconductor channel. In an embodiment, the IL has a thickness of 1 nm or less and comprises zirconium. In an embodiment, a gate dielectric is over the IL, and a gate metal over the gate dielectric.

公开(公告)号：US20200313075A1

公开(公告)日：2020-10-01

申请号：US16367129

申请日：2019-03-27

Applicant: Intel Corporation

Inventor： Noriyuki SATO ,  Angeline SMITH ,  Tanay GOSAVI ,  Sasikanth MANIPATRUNI ,  Kaan OGUZ ,  Kevin O'Brien ,  Benjamin BUFORD ,  Tofizur RAHMAN ,  Rohan PATIL ,  Nafees KABIR ,  Michael CHRISTENSON ,  Ian YOUNG ,  Hui Jae YOO ,  Christopher WIEGAND

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/10 ,  G11C11/16 ,  H01F10/32

Abstract: A memory device includes a first electrode including a spin-orbit material, a magnetic junction on a portion of the first electrode and a first structure including a dielectric on a portion of the first electrode. The first structure has a first sidewall and a second sidewall opposite to the first sidewall. The memory device further includes a second structure on a portion of the first electrode, where the second structure has a sidewall adjacent to the second sidewall of the first structure. The memory device further includes a first conductive interconnect above and coupled with each of the magnetic junction and the second structure and a second conductive interconnect below and coupled with the first electrode, where the second conductive interconnect is laterally distant from the magnetic junction and the second structure.

公开(公告)号：US20200312908A1

公开(公告)日：2020-10-01

申请号：US16367133

申请日：2019-03-27

Applicant: Intel Corporation

Inventor： Kaan OGUZ ,  Christopher WIEGAND ,  Noriyuki SATO ,  Angeline SMITH ,  Tanay GOSAVI

IPC: H01L27/22 ,  H01L43/14

Abstract: A spin orbit memory device includes a material layer stack on a spin orbit electrode. The material layer stack includes a magnetic tunnel junction (MTJ) and a synthetic antiferromagnetic (SAF) structure on the MTJ. The SAF structure includes a first magnet structure and a second magnet structure separated by an antiferromagnetic coupling layer. The first magnet structure includes a first magnet and a second magnet separated by a single layer of a non-magnetic material such as platinum. The second magnet structure includes a stack of bilayers, where each bilayer includes a layer of platinum on a layer of a magnetic material such.

公开(公告)号：US20200227105A1

公开(公告)日：2020-07-16

申请号：US16246362

申请日：2019-01-11

Applicant: Intel Corporation

Inventor： Tanay GOSAVI ,  Sasikanth MANIPATRUNI ,  Chia-Ching LIN ,  Kaan OGUZ ,  Ian YOUNG

IPC: G11C11/16 ,  H01L43/12 ,  H01L43/10 ,  H01L43/08 ,  H01L43/02

Abstract: A memory device includes a spin orbit electrode structure having a dielectric structure including a first sidewall, a second sidewall opposite to the first sidewall, a top surface. The spin orbit electrode structure further includes an electrode having a spin orbit material adjacent to the dielectric structure, where the electrode has a first electrode portion on the top surface, a second electrode portion adjacent to the first sidewall and a third electrode portion adjacent to the second sidewall. The first electrode portion, the second electrode portion and the third electrode portion are contiguous. The spin orbit electrode structure further includes a conductive interconnect in contact with the second electrode portion or the third electrode portion. The memory device further includes a magnetic junction device on a portion of the top surface of the first electrode portion.