公开(公告)号：US20240063120A1

公开(公告)日：2024-02-22

申请号：US17820961

申请日：2022-08-19

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Shawna M. Liff ,  Debendra Mallik ,  Christopher M. Pelto ,  Kimin Jun ,  Johanna M. Swan ,  Lei Jiang ,  Feras Eid ,  Krishna Vasanth Valavala ,  Henning Braunisch ,  Patrick Morrow ,  William J. Lambert

IPC: H01L23/528 ,  H01L23/00 ,  H01L25/065 ,  H01L23/48 ,  H01L23/498 ,  H01L23/522 ,  H01L21/48

CPC classification number: H01L23/5286 ,  H01L24/08 ,  H01L24/05 ,  H01L24/16 ,  H01L25/0652 ,  H01L23/481 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/5283 ,  H01L23/5226 ,  H01L24/80 ,  H01L21/4853 ,  H01L21/4857 ,  H01L2924/37001 ,  H01L2924/3841 ,  H01L2924/3512 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/05647 ,  H01L2224/05687 ,  H01L2224/08121 ,  H01L2224/08145 ,  H01L2224/08225 ,  H01L2224/16225

Abstract: Embodiments of a microelectronic assembly comprise: a plurality of layers of integrated circuit (IC) dies, each layer coupled to adjacent layers by first interconnects having a pitch of less than 10 micrometers between adjacent first interconnects; an end layer in the plurality of layers proximate to a first side of the plurality of layers comprises a dielectric material around IC dies in the end layer and a through-dielectric via (TDV) in the dielectric material of the end layer; a support structure coupled to the first side of the plurality of layers, the support structure comprising a structurally stiff base with conductive traces proximate to the end layer, the conductive traces coupled to the end layer by second interconnects; and a package substrate coupled to a second side of the plurality of layers, the second side being opposite to the first side.

公开(公告)号：US20240061194A1

公开(公告)日：2024-02-22

申请号：US17821019

申请日：2022-08-19

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  David Hui ,  Haris Khan Niazi ,  Wenhao Li ,  Bhaskar Jyoti Krishnatreya ,  Henning Braunisch ,  Shawna M. Liff ,  Jiraporn Seangatith ,  Johanna M. Swan ,  Krishna Vasanth Valavala ,  Xavier Francois Brun ,  Feras Eid

IPC: G02B6/42

CPC classification number: G02B6/4274 ,  G02B6/4204

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include an interconnect die in a first layer surrounded by a dielectric material; a processor integrated circuit (processor IC) and an integrated circuit (IC) in a second layer, the second layer on the first layer, wherein the interconnect die is electrically coupled to the processor IC and the IC by first interconnects having a pitch of less than 10 microns between adjacent first interconnects; a photonic integrated circuit (PIC) and a substrate in a third layer, the third layer on the second layer, wherein the PIC has an active surface, and wherein the active surface of the PIC is coupled to the IC by second interconnects having a pitch of less than 10 microns between adjacent second interconnects; and a fiber connector optically coupled to the active surface of the PIC.

公开(公告)号：US20240063091A1

公开(公告)日：2024-02-22

申请号：US17891735

申请日：2022-08-19

Applicant: Intel Corporation

Inventor： Adel Elsherbini ,  Feras Eid ,  Scot Kellar ,  Yoshihiro Tomita ,  Rajiv Mongia ,  Kimin Jun ,  Shawna Liff ,  Wenhao Li ,  Johanna Swan ,  Bhaskar Jyoti Krishnatreya ,  Debendra Mallik ,  Krishna Vasanth Valavala ,  Lei Jiang ,  Xavier Brun ,  Mohammad Enamul Kabir ,  Haris Khan Niazi ,  Jiraporn Seangatith ,  Thomas Sounart

IPC: H01L23/473 ,  H01L23/00 ,  H01L25/065 ,  H01L23/367 ,  H01L23/373

CPC classification number: H01L23/473 ,  H01L24/08 ,  H01L25/0652 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L23/3677 ,  H01L23/3675 ,  H01L23/3732 ,  H01L23/3738 ,  H01L2924/3511 ,  H01L2224/08145 ,  H01L2224/08121 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/182 ,  H01L2924/186

Abstract: Microelectronic devices, assemblies, and systems include a multichip composite device having one or more chiplets bonded to a base die and an inorganic dielectric material adjacent the chiplets and over the base die. The multichip composite device is coupled to a structural member that is made of or includes a heat conducting material, or has integrated fluidic cooling channels to conduct heat from the chiplets and the base die.

公开(公告)号：US11694942B2

公开(公告)日：2023-07-04

申请号：US16168534

申请日：2018-10-23

Applicant: Intel Corporation

Inventor： Kelly Lofgreen ,  Chandra Mohan Jha ,  Krishna Vasanth Valavala

IPC: H01L23/38 ,  H10N10/01 ,  H10N10/17 ,  H10N10/851 ,  H10N19/00 ,  H01L23/00 ,  H01L25/00 ,  H01L23/48 ,  H01L25/16

CPC classification number: H01L23/38 ,  H10N10/01 ,  H10N10/17 ,  H10N10/851 ,  H10N19/101 ,  H01L23/481 ,  H01L24/09 ,  H01L25/165 ,  H01L25/50 ,  H01L2924/1432 ,  H01L2924/1434

Abstract: An integrated circuit (IC) package comprising an IC die, the IC die having a first surface and an opposing second surface. The IC die comprises a semiconductor material. The first surface comprises an active layer. A thermoelectric cooler (TEC) comprising a thermoelectric material is embedded within the IC die between the first surface and the second surface and adjacent to the active layer. The TEC has an annular shape that is substantially parallel to the first and second surfaces of the IC die. The thermoelectric material is confined between an outer sidewall along an outer perimeter of the TEC and an inner sidewall along an inner perimeter of the TEC. The outer and inner sidewalls are substantially orthogonal to the first and second surfaces of the IC die.

公开(公告)号：US11664293B2

公开(公告)日：2023-05-30

申请号：US16665621

申请日：2019-10-28

Applicant: Intel Corporation

Inventor： Krishna Vasanth Valavala ,  Ravindranath V. Mahajan ,  Chandra Mohan Jha

IPC: H01L23/38 ,  H01L23/42 ,  H01L23/367 ,  H01L23/10 ,  H01L21/48 ,  H01L25/065 ,  H01L23/00

CPC classification number: H01L23/38 ,  H01L21/4871 ,  H01L23/10 ,  H01L23/367 ,  H01L23/42 ,  H01L24/16 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2224/16225

Abstract: Embodiments include a semiconductor package with a thermoelectric cooler (TEC), a method to form such semiconductor package, and a semiconductor packaged system. The semiconductor package includes a die with a plurality of backend layers on a package substrate. The backend layers couple the die to the package substrate. The semiconductor package includes the TEC in the backend layers of the die. The TEC includes a plurality of N-type layers, a plurality of P-type layers, and first and second conductive layers. The first conductive layer is directly coupled to outer regions of bottom surfaces of the N-type and P-type layers, and the second conductive layer is directly coupled to inner regions of top surfaces of the N-type and P-type layers. The first conductive layer has a width greater than a width of the second conductive layer. The N-type and P-type layers are directly disposed between the first and second conductive layers.

公开(公告)号：US20230081139A1

公开(公告)日：2023-03-16

申请号：US17475726

申请日：2021-09-15

Applicant: Intel Corporation

Inventor： Krishna Vasanth Valavala ,  Chandra Mohan Jha ,  Andrew Paul Collins ,  Omkar G. Karhade

IPC: H01L23/538 ,  H01L25/065 ,  H01L25/18 ,  H01L23/367 ,  H01L25/00

Abstract: An example microelectronic assembly includes a substrate, a bridge die over the substrate, and a die stack between the substrate and the bridge die, the die stack including a logic die and at least one memory die, where the logic die is between the at least one memory die and the bridge die.