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    Copper seed layer and nickel-tin microbump structures
    15.
    发明授权
    Copper seed layer and nickel-tin microbump structures 有权

    公开(公告)号：US10297563B2

    公开(公告)日：2019-05-21

    申请号：US15267065

    申请日：2016-09-15

    Applicant: Intel Corporation

    Inventor： Rahul Jain ,  Kyu Oh Lee ,  Amanda E. Schuckman ,  Steve S. Cho

    IPC: H01L23/00

    Abstract: Techniques and mechanisms for providing effective connectivity with surface level microbumps on an integrated circuit package substrate. In an embodiment, different metals are variously electroplated to form a microbump which extends through a surface-level dielectric of a substrate to a seed layer including copper. The microbump includes nickel and tin, wherein the nickel aids in mitigating an absorption of seed layer copper. In another embodiment, the microbump has a mass fraction of tin, or a mass fraction of nickel, that is different in various regions along a height of the microbump.

    Methods of forming sensor integrated packages and structures formed thereby
    17.
    发明授权
    Methods of forming sensor integrated packages and structures formed thereby 有权
    形成传感器集成封装和由此形成的结构的方法

    公开(公告)号：US09505607B2

    公开(公告)日：2016-11-29

    申请号：US14671549

    申请日：2015-03-27

    Applicant: Intel Corporation

    Inventor： Kyu Oh Lee ,  Zheng Zhou ,  Islam A. Salama ,  Feras Eid ,  Sasha N. Oster ,  Lay Wai Kong ,  Javier Soto Gonzalez

    IPC: B81B3/00 ,  B81C1/00

    CPC classification number: B81B7/0077 ,  B81C2203/0109

    Abstract: Methods of forming sensor integrated package devices and structures formed thereby are described. An embodiment includes providing a substrate core, wherein a first conductive trace structure and a second conductive trace structure are disposed on the substrate core, forming a cavity between the first conductive trace structure and the second conductive trace structure, and placing a magnet on a resist material disposed on a portion of each of the first and second conductive trace structures, wherein the resist material does not extend over the cavity.

    Abstract translation: 描述形成传感器集成封装器件和由此形成的结构的方法。 一个实施例包括提供衬底芯，其中第一导电迹线结构和第二导电迹线结构设置在衬底芯上，在第一导电迹线结构和第二导电迹线结构之间形成空腔，并将磁体放置在抗蚀剂上 设置在第一和第二导电迹线结构中的每一个的一部分上的材料，其中抗蚀剂材料不在空腔上延伸。

    IN-PACKAGE TEMPERATURE SENSOR AND METHODS THEREFOR
    19.
    发明申请
    IN-PACKAGE TEMPERATURE SENSOR AND METHODS THEREFOR 审中-公开
    内包温度传感器及其方法

    公开(公告)号：US20150355035A1

    公开(公告)日：2015-12-10

    申请号：US14296782

    申请日：2014-06-05

    Applicant: Intel Corporation

    Inventor： Feras Eid ,  Sasha Oster ,  Sarah Haney ,  Kyu Oh Lee

    IPC: G01K11/26

    CPC classification number: G01K7/32 ,  Y10T29/4913

    Abstract: This disclosure relates generally to an electronic assembly and methods that include a dielectric material forming a cavity, a magnet positioned to induce a magnetic field within the cavity, a conductive trace positioned, at least in part, within the cavity, and a frequency detection circuit configured to detect the frequency of the maximal electromotive force as induced and produce an output proportional to a temperature of the conductive trace. The conductive trace resonates within the cavity based on a temperature-dependent resonant frequency of the conductive trace and a sinusoidal current induced through the conductive trace by a current source, the sinusoidal current induces a maximal electromotive force when a frequency of the sinusoidal current has an approximately equal magnitude to the temperature-dependent resonant frequency of the conductive trace, and the maximal electromotive force, as induced, has a substantially equal frequency as the temperature-dependent resonant frequency of the conductive trace.

    Abstract translation: 本公开总体上涉及电子组件和方法，其包括形成空腔的介电材料，定位成在空腔内引起磁场的磁体，至少部分地位于空腔内的导电迹线，以及频率检测电路 被配置为检测最大电动势的频率，并且产生与导电迹线的温度成比例的输出。 导电迹线基于导电迹线的依赖于​​温度的谐振频率和通过电流源通过导电迹线感应的正弦电流在谐振腔内谐振，当正弦电流的频率具有正弦电流时，正弦电流感应出最大电动势 与导电迹线的温度相关的谐振频率大致相等，并且如感应的最大电动势具有与导电迹线的温度相关的谐振频率基本上相等的频率。

    Magnetic inductor device and method
    20.
    发明授权
    Magnetic inductor device and method 有权

    公开(公告)号：US12224253B2

    公开(公告)日：2025-02-11

    申请号：US17480064

    申请日：2021-09-20

    Applicant: Intel Corporation

    Inventor： Xin Ning ,  Brandon C. Marin ,  Kyu Oh Lee ,  Siddharth K. Alur ,  Numair Ahmed ,  Brent Williams ,  Mollie Stewart ,  Nathan Ou ,  Cary Kuliasha

    IPC: H01L23/64 ,  H01F27/28 ,  H01L21/48 ,  H01L23/498 ,  H01L49/02

    Abstract: Transmission pathways in substrates, and associated methods are shown. Example transmission pathways include a semiconductor substrate with a core, a dielectric layer fixed on the core, at least one first electrical transmission pathway extending through at least one of the dielectric layer and the core. The first pathway includes a magnetic material disposed within the at least the core of the at least one first electrical transmission pathway, at least one second electrical transmission pathway extending through the magnetic material, a nickel layer disposed on inner circumferential surface of the magnetic material at least within the second electrical transmission pathway, a copper layer disposed on at least the nickel layer within the second electrical transmission pathway. The dielectric spacer or the nickel layer separates the copper layer from the magnetic material. At least one third pathway extends through at least one of the dielectric layer and the core separate from the at least one electrical transmission pathway.

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