公开(公告)号：US20210020537A1

公开(公告)日：2021-01-21

申请号：US16516692

申请日：2019-07-19

Applicant: Intel Corporation

Inventor： Sergio Antonio Chan Arguedas ,  Manish Dubey ,  Peng Li ,  Aravindha R. Antoniswamy ,  Anup Pancholi

IPC: H01L23/367 ,  H01L23/00

Abstract: Embodiments may relate to a microelectronic package that includes a die coupled with a package substrate. A solder thermal interface material (STIM) may be coupled with the die such that the die is between the STIM and the package substrate. An integrated heat spreader (IHS) may be coupled with the STIM such that the STIM is between the IHS and the die, and the IHS may include a feature that is to control bleed-out of the STIM during STIM reflow based on surface tension of the STIM. Other embodiments may be described or claimed.

公开(公告)号：US09887104B2

公开(公告)日：2018-02-06

申请号：US14323077

申请日：2014-07-03

Applicant: Intel Corporation

Inventor： Manish Dubey ,  Rajendra C. Dias ,  Patrick Nardi ,  David Woodhams

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/24 ,  H01L23/00

CPC classification number: H01L21/563 ,  H01L23/24 ,  H01L24/32 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/83951 ,  H01L2924/15311 ,  H01L2924/00

Abstract: Some embodiments relate to an electronic package. The electronic package includes a substrate and a die attached to the substrate. The electronic package further includes an underfill positioned between the die and the substrate due to capillary action. A support surrounds the die. The support provides the same beneficial fillet geometry on all die edges. Therefore, the support provides similar stress reduction on all die edges. Other embodiments relate to method of fabricating an electronic package. The method includes attaching a die to a substrate and inserting an underfill between the die and the substrate using capillary action. The method further includes placing a support around the die such that the support surrounds the die.

公开(公告)号：US20160233175A1

公开(公告)日：2016-08-11

申请号：US14618647

申请日：2015-02-10

Applicant: Intel Corporation

Inventor： Manish Dubey ,  Emre Armagan ,  Rajendra C. Dias ,  Lars D. Skoglund

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/12 ,  H01L21/304 ,  H01L29/06 ,  H01L23/31

CPC classification number: H01L23/562 ,  H01L21/304 ,  H01L21/563 ,  H01L23/12 ,  H01L23/3157 ,  H01L29/06 ,  H01L2224/73204

Abstract: A microelectronic die may be formed with chamfer corners for reducing stresses which can lead to delamination and/or cracking failures when such a microelectronic die is incorporated into a microelectronic package. In one embodiment, a microelectronic die may include at least one substantially planar chamfering side extending between at least two adjacent sides of a microelectronic die. In another embodiment, a microelectronic die may include at least one substantially curved or arcuate chamfering side extending between at least two adjacent sides of a microelectronic die.

Abstract translation: 可以形成具有倒角的微电子模具，用于减小当将这种微电子管芯并入微电子封装时可能导致分层和/或破裂故障的应力。 在一个实施例中，微电子管芯可以包括在微电子管芯的至少两个相邻侧面之间延伸的至少一个基本上平面的倒角侧。 在另一个实施例中，微电子管芯可以包括在微电子管芯的至少两个相邻侧面之间延伸的至少一个基本上弯曲或弧形的倒角侧。

公开(公告)号：US08999765B2

公开(公告)日：2015-04-07

申请号：US13925967

申请日：2013-06-25

Applicant: Intel Corporation

Inventor： Manish Dubey ,  Rajendra C. Dias ,  Yonghao Xiu ,  Arjun Krishnan ,  Yiqun Bai ,  Purushotham Kaushik Muthur Srinath

IPC: H01L23/488 ,  H01L21/56

CPC classification number: H01L21/563 ,  H01L23/00 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments of the present description include methods for attaching a microelectronic device to a microelectronic substrate with interconnection structures after disposing of an underfill material on the microelectronic device, wherein filler particles within the underfill material may be repelled away from the interconnection structures prior to connecting the microelectronic device to the microelectronic structure. These methods may include inducing a charge on the interconnection structures and may include placing the interconnection structures between opposing plates and producing a bias between the opposing plates after depositing the underfill material on the interconnection structures.

Abstract translation: 本说明书的实施例包括在微电子器件上处理底部填充材料之后，将微电子器件附着到具有互连结构的微电子衬底的方法，其中在将微电子器件连接到底部填充材料之前，底部填充材料内的填料颗粒可能被排除离开互连结构 器件到微电子结构。 这些方法可以包括在互连结构上引入电荷，并且可以包括将互连结构放置在相对的板之间，并且在将底部填充材料沉积在互连结构上之后在相对的板之间产生偏压。

公开(公告)号：US11887962B2

公开(公告)日：2024-01-30

申请号：US16902927

申请日：2020-06-16

Applicant: Intel Corporation

Inventor： Omkar G. Karhade ,  Nitin A. Deshpande ,  Mohit Bhatia ,  Sairam Agraharam ,  Edvin Cetegen ,  Anurag Tripathi ,  Malavarayan Sankarasubramanian ,  Jan Krajniak ,  Manish Dubey ,  Jinhe Liu ,  Wei Li ,  Jingyi Huang

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L24/30 ,  H01L23/49827 ,  H01L23/5384 ,  H01L24/17 ,  H01L2224/1703

Abstract: Disclosed herein are microelectronic structures including bridges, as well as related assemblies and methods. In some embodiments, a microelectronic structure may include a substrate and a bridge.

公开(公告)号：US20240030142A1

公开(公告)日：2024-01-25

申请号：US18375867

申请日：2023-10-02

Applicant: Intel Corporation

Inventor： Sanka Ganesan ,  Ram Viswanath ,  Xavier Francois Brun ,  Tarek A. Ibrahim ,  Jason M. Gamba ,  Manish Dubey ,  Robert Alan May

IPC: H01L23/538 ,  H01L23/367 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L23/5381 ,  H01L23/367 ,  H01L23/3185 ,  H01L23/5386 ,  H01L24/16 ,  H01L23/5384 ,  H01L2224/16227

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic component may include a substrate having a first face and an opposing second face, wherein the substrate includes a through-substrate via (TSV); a first mold material region at the first face, wherein the first mold material region includes a first through-mold via (TMV) conductively coupled to the TSV; and a second mold material region at the second face, wherein the second mold material region includes a second TMV conductively coupled to the TSV.

公开(公告)号：US20200227332A1

公开(公告)日：2020-07-16

申请号：US16244748

申请日：2019-01-10

Applicant: Intel Corporation

Inventor： Kumar Abhishek Singh ,  Omkar Karhade ,  Nitin Deshpande ,  Mitul Modi ,  Edvin Cetegen ,  Aastha Uppal ,  Debendra Mallik ,  Sanka Ganesan ,  Yiqun Bai ,  Jan Krajniak ,  Manish Dubey ,  Ravindranath Mahajan ,  Ram Viswanath ,  James C. Matayabas, JR.

IPC: H01L23/34 ,  H01L23/31 ,  H01L23/00 ,  H01L21/56 ,  H01L21/48 ,  H01L23/48

Abstract: An integrated circuit package may be formed having at least one heat dissipation structure within the integrated circuit package itself. In one embodiment, the integrated circuit package may include a substrate; at least one integrated circuit device, wherein the at least one integrated circuit device is electrically attached to the substrate; a mold material on the substrate and adjacent to the at least one integrated circuit device; and at least one heat dissipation structure contacting the at least one integrated circuit, wherein the at least one heat dissipation structure is embedded either within the mold material or between the mold material and the substrate.

公开(公告)号：US10535615B2

公开(公告)日：2020-01-14

申请号：US15548741

申请日：2016-02-12

Applicant: Intel Corporation

Inventor： Manish Dubey ,  Srikant Nekkanty ,  Rajendra C. Dias ,  Patrick Nardi

IPC: H01L23/16 ,  H01L23/00 ,  H01L23/498 ,  H01L23/58

Abstract: An electronic package that includes a substrate and a die attached to the substrate. The electronic package further includes a stiffener that is attached to the substrate adjacent to the die. The stiffener is formed of a first layer made from one material and a second layer made from a different material.

公开(公告)号：US20180033741A1

公开(公告)日：2018-02-01

申请号：US15548741

申请日：2016-02-12

Applicant: Intel Corporation

Inventor： Manish Dubey ,  Srikant Nekkanty ,  Rajendra C. Dias ,  Patrick Nardi

IPC: H01L23/00 ,  H01L23/498 ,  H01L23/58

CPC classification number: H01L23/562 ,  H01L23/16 ,  H01L23/498 ,  H01L23/49838 ,  H01L23/585 ,  H01L2924/3511

Abstract: An electronic package that includes a substrate and a die attached to the substrate. The electronic package further includes a stiffener that is attached to the substrate adjacent to the die. The stiffener is formed of a first layer made from one material and a second layer made from a different material.

公开(公告)号：US20170018525A1

公开(公告)日：2017-01-19

申请号：US15121295

申请日：2014-03-28

Applicant: INTEL CORPORATION

Inventor： Rajendra C. Dias ,  Manish Dubey ,  Emre Armagan

IPC: H01L23/00

CPC classification number: H01L24/81 ,  H01L21/4853 ,  H01L23/49811 ,  H01L23/5383 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/742 ,  H01L2224/0214 ,  H01L2224/0312 ,  H01L2224/0333 ,  H01L2224/0381 ,  H01L2224/0401 ,  H01L2224/05571 ,  H01L2224/10175 ,  H01L2224/11003 ,  H01L2224/113 ,  H01L2224/1132 ,  H01L2224/1147 ,  H01L2224/13007 ,  H01L2224/13017 ,  H01L2224/131 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13184 ,  H01L2224/1601 ,  H01L2224/16013 ,  H01L2224/16014 ,  H01L2224/16057 ,  H01L2224/16058 ,  H01L2224/16059 ,  H01L2224/16111 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/742 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/81385 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81484 ,  H01L2224/81815 ,  H01L2924/15192 ,  H01L2924/381 ,  H01L2924/3841 ,  H01L2924/40102 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00012

Abstract: A method for attaching an integrated circuit (IC) to an IC package substrate includes forming a solder bump on a bond pad of an IC die, forming a solder-wetting protrusion on a bond pad of an IC package substrate, and bonding the solder bump of the IC die to the solder-wetting protrusion of the IC package substrate.

Abstract translation: 一种将集成电路（IC）附着到IC封装基板的方法包括在IC芯片的焊盘上形成焊料凸块，在IC封装基板的焊盘上形成焊料润湿突起，并将焊料凸块 的IC管芯到IC封装衬底的焊料润湿突起。