公开(公告)号：US20190042357A1

公开(公告)日：2019-02-07

申请号：US16141862

申请日：2018-09-25

Applicant: INTEL CORPORATION

Inventor： Wei WU

IPC: G06F11/10 ,  H03M13/15 ,  G11C29/52

Abstract: Provided are an apparatus, memory device, and method to determine error location polynomial coefficients to provide to bit correction logic instances to decode bits of a codeword. A memory controller for a memory includes coefficient generating logic to receive as input a plurality of syndrome values to generate a plurality of coefficients for an error locator polynomial. A plurality of instances of bit correction logic, one instance for each bit of bits to correct in a codeword for a block in the memory array to decode. Each instance of bit correction logic is to receive as input the coefficients for the error locator polynomial and elements for the bit to correct from a decoder alphabet to determine whether to correct the bit and output as a decoded bit the bit or a corrected bit to include in a decoded codeword.

公开(公告)号：US20180082176A1

公开(公告)日：2018-03-22

申请号：US15273505

申请日：2016-09-22

Applicant: INTEL CORPORATION

Inventor： Wei WU ,  Charles AUGUSTINE ,  Somnath PAUL

IPC: G06N3/063 ,  G06N3/04

CPC classification number: G06N3/063 ,  G06N3/049 ,  G06N3/088

Abstract: Provided are a neuromorphic computing device, memory device, system, and method to maintain a spike history for neurons in a spiking neural network. A neural network spike history is generated in a memory device having an array of rows and columns of memory cells. There is one row of the rows for each of a plurality of neurons and columns for each of a plurality of time slots. Indication is made in a current column in the row of the memory cells for a firing neuron that a spike was fired. Indication is made in the current column in rows of memory cells of idle neurons that did not fire that a spike was not fired. Information in the array is used to determine a timing difference between a connected neuron and the firing neuron and to adjust a weight of the connecting synapse.

公开(公告)号：US20240061741A1

公开(公告)日：2024-02-22

申请号：US18268956

申请日：2020-12-26

Applicant: Intel Corporation

Inventor： Rajat AGARWAL ,  Hsing-Min CHEN ,  Wei P. CHEN ,  Wei WU ,  Jing LING ,  Kuljit S. BAINS ,  Kjersten E. CRISS ,  Deep K. BUCH ,  Theodros YIGZAW ,  John G. HOLM ,  Andrew M. RUDOFF ,  Vaibhav SINGH ,  Sreenivas MANDAVA

IPC: G06F11/10

CPC classification number: G06F11/10

Abstract: A memory subsystem includes memory devices with space dynamically allocated for improvement of reliability, availability, and serviceability (RAS) in the system. Error checking and correction (ECC) logic detects an error in all or a portion of a memory device. In response to error detection, the system can dynamically perform one or more of: allocate active memory device space for sparing to spare a failed memory segment; write a poison pattern into a failed cacheline to mark it as failed; perform permanent fault detection (PFD) and adjust application of ECC based on PFD detection; or, spare only a portion of a device and leave another portion active, including adjusting ECC based on the spared portion. The error detection can be based on bits of an ECC device, and error correction based on those bits and additional bits stored on the data devices.

公开(公告)号：US20210019225A1

公开(公告)日：2021-01-21

申请号：US17031772

申请日：2020-09-24

Applicant: Intel Corporation

Inventor： Byoungchan OH ,  Wei WU

IPC: G06F11/10 ,  H03M13/15 ,  H03M13/29

Abstract: Examples include techniques to improve implement an error correction codeword (ECC) scheme to protect data stored to a memory from both hard and random bit errors using a hybrid ECC scheme that includes generation of first and second codewords to protect the data.

公开(公告)号：US20170177519A1

公开(公告)日：2017-06-22

申请号：US14975293

申请日：2015-12-18

Applicant: INTEL CORPORATION

Inventor： Wei WU ,  Shigeki TOMISHIMA ,  Shih-Lien L. LU

IPC: G06F13/28 ,  G06F13/16 ,  G06F13/40

CPC classification number: G06F13/28 ,  G06F13/1668 ,  G06F13/4027

Abstract: Provided are a memory device and a memory bank comprising a split local data bus, and a segmented global data bus coupled to local data bus. Provided also is a method comprising, receiving a signal from a split local data bus, and transmitting the signal to a segmented global data bus coupled to local data bus. Provided also is a computational device that includes the memory device and the memory bank, and optionally one or more of a display, a network interface, and a battery.

公开(公告)号：US20170153933A1

公开(公告)日：2017-06-01

申请号：US15374922

申请日：2016-12-09

Applicant: Intel Corporation

Inventor： Shigeki TOMISHIMA ,  Charles AUGUSTINE ,  Wei WU ,  Shih Lien L. LU

IPC: G06F11/07 ,  G11C11/16 ,  G06F3/06 ,  H03M13/15 ,  H03M13/37 ,  G11C13/00 ,  G06F11/10

CPC classification number: G06F11/073 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0679 ,  G06F11/0751 ,  G06F11/079 ,  G06F11/0793 ,  G06F11/1048 ,  G06F11/1076 ,  G11C11/1655 ,  G11C11/1659 ,  G11C11/1673 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/004 ,  G11C29/42 ,  G11C29/52 ,  G11C2013/0042 ,  G11C2213/79 ,  G11C2213/82 ,  H03M13/1575 ,  H03M13/373 ,  H03M13/6502

Abstract: Described is an apparatus which comprises: a complementary resistive memory bit-cell; a first sense amplifier coupled to the complementary resistive memory bit-cell via access devices; a second sense amplifier coupled to the first sense amplifier and to the complementary resistive memory bit-cell via the access devices, wherein the second sense amplifier is operable to detect an error in the complementary resistive memory bit-cell.

公开(公告)号：US20210294799A1

公开(公告)日：2021-09-23

申请号：US17341963

申请日：2021-06-08

Applicant: Intel Corporation

Inventor： Wei WU ,  Sourabh DONGAONKAR ,  Jawad B. KHAN

IPC: G06F16/2458 ,  G06F16/248 ,  G06F16/22 ,  G06N3/04

Abstract: Methods and apparatus for sparse column-aware encodings for numeric data types, including integer data and floating-point data (float, double, etc.). The encoding schemes are tailored to take advantage of column addressable memories such as stochastic associative memories (SAM) to enable Stochastic Associative Search (SAS), which is a highly efficient and fast way of searching through a very large database of records (order of Billions) and finding similar records to a given query record (search key). Techniques are also disclosed for performing range searches for both integer and floating-point data types. The integer or float data is converted to Hexadecimal form and encoded using an m-of-n constant weight encoding. Only the columns with set bits in search keys need to be read, which significantly reduces the number of reads required for searches.

公开(公告)号：US20190044536A1

公开(公告)日：2019-02-07

申请号：US16022631

申请日：2018-06-28

Applicant: Intel Corporation

Inventor： Jawad B. KHAN ,  Sanjeev N. TRIKA ,  Omesh Tickoo ,  Wei WU

IPC: H03M13/05 ,  G06F11/10 ,  H03M13/00

CPC classification number: H03M13/05 ,  G06F11/1044 ,  G06F11/1048 ,  H03M13/611

Abstract: To address the storage needs of applications that work with noisy data (e.g. image, sound, video data), where errors can be tolerated to a certain extent and performance is more critical than data fidelity, dynamic reliability levels enable storage devices capable of storing and retrieving data with varying degrees of data fidelity to dynamically change the degree of data fidelity in response to an application's request specifying reliability level. By allowing the application to specify the reliability level at which its data is stored and retrieved, dynamic reliability levels can increase read/write performance without sacrificing application accuracy. The application can specify reliability levels for different types or units of data, such as different reliability levels for metadata as opposed to data and so forth.

公开(公告)号：US20180218759A1

公开(公告)日：2018-08-02

申请号：US15940811

申请日：2018-03-29

Applicant: INTEL CORPORATION

Inventor： Wei WU ,  Shigeki TOMISHIMA ,  Shih-Lien L. LU

IPC: G11C7/06 ,  G11C11/406 ,  G11C7/10 ,  G06F13/40 ,  G06F13/42 ,  G06F13/16

CPC classification number: G11C7/06 ,  G06F13/1678 ,  G06F13/4018 ,  G06F13/4282 ,  G11C7/1048 ,  G11C7/1072 ,  G11C11/40618 ,  G11C11/4091 ,  G11C11/4093 ,  G11C2207/105 ,  G11C2207/107

Abstract: Provided is memory device and a memory bank, comprising a global data bus, and a local data bus split into two parts, wherein the local data bus is configurable to direct signals to the global data bus. Provided also is a method in which signals are received in a local data bus that is split into two parts, and the signals are directed from the local data bus to the global data bus. Provided also is a computational device comprised of a processor and the memory device.

公开(公告)号：US20170286221A1

公开(公告)日：2017-10-05

申请号：US15086050

申请日：2016-03-30

Applicant: INTEL CORPORATION

Inventor： Tal AZOGUI ,  Vered BAR BRACHA ,  Vallabhajosyula S. SOMAYAZULU ,  Wei WU

IPC: G06F11/10 ,  G06F3/06

CPC classification number: G06F3/067 ,  G06F3/0619 ,  G06F3/064 ,  G06F11/1048

Abstract: Provided are a method and apparatus for an error tolerance aware data retention scheme in a storage device for multi-scale error tolerant data. A mapping of retention priorities to sectors of the storage units maps higher retention priorities to sectors having a higher retention capability. A data stream and retention metadata for the data stream indicate retention priorities for segments of the data stream. Segments of the data stream having less error tolerance are mapped to higher retention priorities than segments of the data stream having greater error tolerance. The mapping of retention priorities is used to determine a sector having a retention priority matching a retention priority of a segment of the data stream indicated in the retention metadata. The segment of the data stream is stored in the determined sector.