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公开(公告)号：US20240107900A1
公开(公告)日：2024-03-28
申请号：US17934212
申请日：2022-09-22
发明人： Juntao Li , Kangguo Cheng , Carl Radens , Ching-Tzu Chen
CPC分类号： H01L45/06 , H01L27/2463 , H01L45/126 , H01L45/1286 , H01L45/141 , H01L45/145 , H01L45/1616 , H01L45/1675
摘要： A phase change memory structure with improved sidewall heater and formation thereof may be presented. Phase change materials are capable of being switched between a first structural state in which the material is in a generally amorphous solid phase, and a second structural state in which the material is in a generally crystalline solid phase in the active region of the cell. Presented herein may be a side wall heater, where the upper section extends through bilayer dielectric to contact a phase change material layer and the lower section of the sidewall heater has conductive layers in contact with the bottom electrode. The width of the sidewall heater may reflect an inverted T shape reducing the current requirement to reset the phase change material.
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公开(公告)号：US20240081159A1
公开(公告)日：2024-03-07
申请号：US17929330
申请日：2022-09-02
发明人： Ching-Tzu Chen , Kevin W. Brew , JIN PING HAN , Timothy Mathew Philip , Injo Ok
CPC分类号： H01L45/06 , H01L27/2463 , H01L45/126 , H01L45/1286 , H01L45/1608 , H01L45/1666
摘要： A structure including alternating layers of phase change material layers and dielectric encapsulated heater element layers, the alternating layers of phase change material layers and the dielectric encapsulated heater element layers are sandwiched between a first electrode and a second electrode. A structure including horizontally aligned alternating layers of phase change material layers and dielectric encapsulated heater element layers, the alternating layers of phase change material layers and the dielectric encapsulated heater element layers are sandwiched between a first electrode and a second electrode. A method including forming alternating layers of phase change material layers and dielectric encapsulated heater element layers, the alternating layers of phase change material layers and the dielectric encapsulated heater element layers are sandwiched between a first electrode and a second electrode.
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公开(公告)号：US11749602B2
公开(公告)日：2023-09-05
申请号：US16950453
申请日：2020-11-17
IPC分类号： H01L23/532 , H01L23/522 , H01L21/3213 , H01L21/768 , H01L23/528
CPC分类号： H01L23/53209 , H01L21/3213 , H01L21/76831 , H01L23/5226 , H01L23/5283
摘要： Provided is a method for fabricating an interconnect. The method comprises forming a topological semi-metal layer. The method further comprises patterning the topological semi-metal layer to form one or more interconnects. The method further comprises forming a dielectric layer between the one or more interconnects. The method further comprises forming a hermetic dielectric cap layer on top of the one or more interconnects and the dielectric layer.
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14.发明授权公开(公告)号：US09601685B1
公开(公告)日：2017-03-21
申请号：US15183172
申请日：2016-06-15
IPC分类号： H01L43/04 , H01L29/10 , H01L49/00 , H01L29/16 , H01L29/24 , H01L43/06 , G01N27/12 , H01L29/06 , H01L43/14
CPC分类号： H01L43/065 , G01N27/125 , H01L27/22 , H01L29/0649 , H01L29/1029 , H01L29/1606 , H01L29/24 , H01L43/02 , H01L43/04 , H01L43/06 , H01L43/08 , H01L43/10 , H01L43/14 , H01L49/003
摘要： A technique relates to a semiconductor device. First metal contacts are formed on top of a substrate. The first metal contacts are arranged in a first direction, and the first metal contacts are arranged such that areas of the substrate remain exposed. Insulator pads are positioned at predefined locations on top of the first metal contacts, such that the insulator pads are spaced from one another. Second metal contacts are formed on top of the insulator pads, such that the second metal contacts are arranged in a second direction different from the first direction. The first and second metal contacts sandwich the insulator pads at the predefined locations. Surface-sensitive conductive channels are formed to contact the first metal contacts and the second metal contacts. Four-terminal devices are defined by the surface-sensitive conductive channels contacting a pair of the first metal contacts and contacting a pair of the metal contacts.
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公开(公告)号：US09484469B2
公开(公告)日：2016-11-01
申请号：US14571771
申请日：2014-12-16
IPC分类号： H01L29/786 , H01L29/16 , H01L29/06 , H01L21/02 , H01L21/283 , H01L29/20 , H01L29/24 , H01L21/04 , H01L51/05 , H01L51/00 , H01L21/441 , H01L29/66
CPC分类号： H01L51/0541 , G01N27/414 , G01N27/4141 , G01N27/4146 , H01L21/02527 , H01L21/0254 , H01L21/02568 , H01L21/02606 , H01L21/043 , H01L21/283 , H01L21/441 , H01L21/7682 , H01L23/53276 , H01L28/60 , H01L29/0665 , H01L29/0673 , H01L29/1606 , H01L29/2003 , H01L29/24 , H01L29/66045 , H01L29/66969 , H01L29/778 , H01L29/78684 , H01L29/78696 , H01L43/08 , H01L51/0048 , H01L51/0558 , H01L2221/1094
摘要： Embodiments of the invention include a method for fabricating a semiconductor device and the resulting structure. A substrate is provided. A plurality of metal portions are formed on the substrate, wherein the plurality of metal portions are arranged such that areas of the substrate remain exposed. A thin film layer is deposited on the plurality of metal portions and the exposed areas of the substrate. A dielectric layer is deposited, wherein the dielectric layer is in contact with portions of the thin film layer on the plurality of metal portions, and wherein the dielectric layer is not in contact with portions of the thin film layer on the exposed areas of the substrate such that one or more enclosed spaces are present between the thin film layer on the exposed areas of the substrate and the dielectric layer.
摘要翻译： 本发明的实施例包括一种用于制造半导体器件的方法及其结果。 提供基板。 在基板上形成多个金属部分，其中多个金属部分被布置成使得基板的区域保持暴露。 在多个金属部分和基板的暴露区域上沉积薄膜层。 沉积介电层，其中电介质层与多个金属部分上的薄膜层的部分接触，并且其中介电层不与衬底的暴露区域上的薄膜层的部分接触 使得在衬底的暴露区域和电介质层之间的薄膜层之间存在一个或多个封闭空间。
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16.发明授权Fabricating two-dimensional array of four-terminal thin film devices with surface-sensitive conductor layer 有权制造具有表面敏感导体层的四端子薄膜器件的二维阵列公开(公告)号：US09406872B1
公开(公告)日：2016-08-02
申请号：US14941878
申请日：2015-11-16
CPC分类号： H01L43/065 , G01N27/125 , H01L27/22 , H01L29/0649 , H01L29/1029 , H01L29/1606 , H01L29/24 , H01L43/02 , H01L43/04 , H01L43/06 , H01L43/08 , H01L43/10 , H01L43/14 , H01L49/003
摘要： A technique relates to a semiconductor device. First metal contacts are formed on top of a substrate. The first metal contacts are arranged in a first direction, and the first metal contacts are arranged such that areas of the substrate remain exposed. Insulator pads are positioned at predefined locations on top of the first metal contacts, such that the insulator pads are spaced from one another. Second metal contacts are formed on top of the insulator pads, such that the second metal contacts are arranged in a second direction different from the first direction. The first and second metal contacts sandwich the insulator pads at the predefined locations. Surface-sensitive conductive channels are formed to contact the first metal contacts and the second metal contacts. Four-terminal devices are defined by the surface-sensitive conductive channels contacting a pair of the first metal contacts and contacting a pair of the metal contacts.
摘要翻译： 技术涉及半导体器件。 第一金属触点形成在基板的顶部。 第一金属触头沿第一方向布置，并且第一金属触点被布置成使得基板的区域保持暴露。 绝缘垫位于第一金属触点顶部的预定位置处，使得绝缘垫彼此间隔开。 第二金属触点形成在绝缘体焊盘的顶部上，使得第二金属触点沿与第一方向不同的第二方向布置。 第一和第二金属触点在预定位置处夹住绝缘体垫。 形成表面敏感导电通道以接触第一金属触点和第二金属触点。 四端子器件由接触一对第一金属触点并接触一对金属触点的表面敏感导电通道限定。
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公开(公告)号：US20240008374A1
公开(公告)日：2024-01-04
申请号：US17855131
申请日：2022-06-30
发明人： Kevin W. Brew , Timothy Mathew Philip , JIN PING HAN , Ching-Tzu Chen , Injo Ok
CPC分类号： H01L45/06 , H01L27/24 , H01L45/1675 , H01L45/144 , H01L45/1616 , H01L45/1253
摘要： Memory cells and methods of forming the same include forming a hole in an interlayer dielectric to expose an end of a conductive top electrode. A phase change material is conformally deposited on surfaces of the hole. A remaining portion of the hole is filled with a dielectric material after conformally depositing the phase change material.
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公开(公告)号：US20230361038A1
公开(公告)日：2023-11-09
申请号：US18354331
申请日：2023-07-18
IPC分类号： H01L23/532 , H01L23/522 , H01L21/3213 , H01L21/768 , H01L23/528
CPC分类号： H01L23/53209 , H01L23/5226 , H01L21/3213 , H01L21/76831 , H01L23/5283
摘要： Provided is a method for fabricating an interconnect. The method comprises forming a topological semi-metal layer. The method further comprises patterning the topological semi-metal layer to form one or more interconnects. The method further comprises forming a dielectric layer between the one or more interconnects. The method further comprises forming a hermetic dielectric cap layer on top of the one or more interconnects and the dielectric layer.
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公开(公告)号：US20230309425A1
公开(公告)日：2023-09-28
申请号：US17656430
申请日：2022-03-25
发明人： Timothy Mathew Philip , JIN PING HAN , Ching-Tzu Chen , Kevin W. Brew , Injo Ok
IPC分类号： H01L45/00
CPC分类号： H01L45/1226 , H01L45/06 , H01L45/1253 , H01L45/16
摘要： A structure including an inner electrode and an outer electrode on a substrate and a phase change material layer, the phase change material layer vertically aligned above both the inner electrode and the outer electrode. A structure including an inner electrode and an outer electrode on a substrate and a phase change material layer, the phase change material layer vertically aligned above both the inner electrode and the outer electrode, where the inner electrode and the outer electrode are on the same horizontal plane. A method including forming an inner electrode and an outer electrode simultaneously on a substrate, forming a phase change material layer above both the inner electrode and the outer electrode.
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20.发明授权公开(公告)号：US11429524B2
公开(公告)日：2022-08-30
申请号：US16785708
申请日：2020-02-10
摘要： Various embodiments are provided for optimized placement of data structures in a hierarchy of memory in a computing environment. One or more data structures may be placed in a first scratchpad memory, a second scratchpad memory, an external memory, or a combination thereof in the hierarchy of memory according to a total memory capacity and bandwidth, a level of reuse of the one or more data structures, a number of operations that use each of the one or more data structures, a required duration each the one or more data structures are required to be placed a first scratchpad or a second scratchpad, and characteristics of those of the one or more data structures competing for placement in the hierarchy of memory that are able to co-exist at a same time step. The second scratchpad memory is positioned between the external memory and the first scratchpad memory at one or more intermediary layers.
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