利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

19 条记录 (耗时 0.031 秒)

    Method of making a read only memory device
    11.
    发明授权
    Method of making a read only memory device 失效
    制作只读存储器件的方法

    公开(公告)号：US4904615A

    公开(公告)日：1990-02-27

    申请号：US301978

    申请日：1989-01-26

    申请人： Kousuke Okuyama ,  Ken Uchida ,  Kouichi Kusuyama ,  Satoshi Meguro ,  Hisao Katto ,  Kazuhiro Komori

    发明人： Kousuke Okuyama ,  Ken Uchida ,  Kouichi Kusuyama ,  Satoshi Meguro ,  Hisao Katto ,  Kazuhiro Komori

    IPC分类号： H01L27/112 ,  H01L21/8246

    CPC分类号： H01L27/1126

    摘要： Disclosed are memory cells of a vertical-type read only memory (ROM) having a plurality of MISFETs connected in series. The MISFETs include gate electrodes formed with multiple conductive layers, in which some of the MISFETs are set to the depletion type and at least some of the remaining MISFETs are set to the enhancement type, so as to write information in the memory cells. The information write operation is conducted through at least two steps. Namely, in the first information write step, gate electrodes are used as a mask to implant an impurity; and in the second step, an impurity is implanted through the gate electrodes into the surface of the semiconductor substrate. These steps enable a semiconductor memory device, such as a vertical-type mask ROM having memory cells with a reduced series resistance and being suitable for a high degree of integration, to be produced.Furthermore, there is disclosed a memory structure of a semiconductor memory device suitable for a higher degree of integration through an arrangement of gate electrodes of multiple layers.

    Method of fabrication of semiconductor integrated circuit device
    15.
    发明授权
    Method of fabrication of semiconductor integrated circuit device 失效
    半导体集成电路器件制造方法

    公开(公告)号：US5610089A

    公开(公告)日：1997-03-11

    申请号：US429868

    申请日：1995-04-27

    申请人： Hidetoshi Iwai ,  Kazumichi Mitsusada ,  Masamichi Ishihara ,  Tetsuro Matsumoto ,  Kazuyuki Miyazawa ,  Hisao Katto ,  Kousuke Okuyama

    发明人： Hidetoshi Iwai ,  Kazumichi Mitsusada ,  Masamichi Ishihara ,  Tetsuro Matsumoto ,  Kazuyuki Miyazawa ,  Hisao Katto ,  Kousuke Okuyama

    IPC分类号： H01L21/8238 ,  H01L21/8242 ,  H01L27/02 ,  H01L27/092 ,  H01L29/78

    CPC分类号： H01L27/10873 ,  H01L21/823864 ,  H01L27/0251 ,  H01L27/0266 ,  H01L27/0922 ,  H01L29/78 ,  H01L29/7836

    摘要： Disclosed is a semiconductor device having an internal circuit protected by an electrostatic protective circuit, the internal circuit and electrostatic protective circuit being formed on the same semiconductor substrate. The internal circuit includes MIS elements and has a double-diffused drain structure, while the protective circuit has a single-diffused drain structure. The internal circuit can be, e.g., a DRAM, and the protective circuit can have diffused resistors and clamping MIS elements. The single-diffused drain structure can be formed in the protective circuit on the semiconductor substrate, while providing double-diffused drain structure in the internal circuit on the same substrate, by: (1) scanning the ion implanting apparatus to avoid ion implantation of the first ions into the region of the protective circuit, and/or (2) forming a photoresist film over the region of the protective circuit to prevent ion implanation of the first ions into the protective circuit region. As a further embodiment of the present invention, a semiconductor integrated circuit device is provided wherein the source and drain regions of an MOSFET in the internal circuit have lightly doped drain (LDD) structure in order to suppress the appearance of hot carriers, and the source and drain regions of an MOSFET in the input/output circuit have structure doped with phosphorus at a high impurity concentration, in order to enhance an electrostatic breakdown voltage.

    摘要翻译： 公开了具有被静电保护电路保护的内部电路的半导体器件，内部电路和静电保护电路形成在同一半导体衬底上。 内部电路包括MIS元件，并具有双扩散漏极结构，而保护电路具有单扩散漏极结构。 内部电路可以是例如DRAM，并且保护电路可以具有扩散电阻器和钳位MIS元件。 单扩散漏极结构可以形成在半导体衬底上的保护电路中，同时通过以下步骤在同一衬底上的内部电路中提供双扩散漏极结构：（1）扫描离子注入装置以避免离子注入 第一离子进入保护电路的区域，和/或（2）在保护电路的区域上形成光致抗蚀剂膜，以防止第一离子离子注入保护电路区域。 作为本发明的另一实施例，提供了一种半导体集成电路器件，其中内部电路中的MOSFET的源极和漏极区域具有轻掺杂漏极（LDD）结构，以便抑制热载流子的出现，源极 并且输入/输出电路中的MOSFET的漏极区域掺杂有高杂质浓度的磷的结构，以增强静电击穿电压。

    Semiconductor integrated circuit device having output and internal circuit MISFETS
    16.
    发明授权
    Semiconductor integrated circuit device having output and internal circuit MISFETS 失效
    具有输出和内部电路MISFETS的半导体集成电路器件

    公开(公告)号：US5534723A

    公开(公告)日：1996-07-09

    申请号：US431568

    申请日：1995-04-27

    申请人： Hidetoshi Iwai ,  Kazumichi Mitsusada ,  Masamichi Ishihara ,  Tetsuro Matsumoto ,  Kazuyuki Miyazawa ,  Hisao Katto ,  Kousuke Okuyama

    发明人： Hidetoshi Iwai ,  Kazumichi Mitsusada ,  Masamichi Ishihara ,  Tetsuro Matsumoto ,  Kazuyuki Miyazawa ,  Hisao Katto ,  Kousuke Okuyama

    IPC分类号： H01L21/8238 ,  H01L21/8242 ,  H01L27/02 ,  H01L27/092 ,  H01L29/78 ,  H01L29/06

    CPC分类号： H01L21/823864 ,  H01L27/0251 ,  H01L27/0266 ,  H01L27/0922 ,  H01L27/10873 ,  H01L29/78

    摘要： Disclosed is a semiconductor device having an internal circuit protected by an electrostatic protective circuit, the internal circuit and electrostatic protective circuit being formed on the same semiconductor substrate. The internal circuit includes MIS elements and has a double-diffused drain structure, while the protective circuit has a single-diffused drain structure. The internal circuit can be, e.g., a DRAM, and the protective circuit can have diffused resistors and clamping MIS elements. The single-diffused drain structure can be formed in the protective circuit on the semiconductor substrate, while providing double-diffused drain structure in the internal circuit on the same substrate, by: (1) scanning the ion implanting apparatus to avoid ion implantation of the first ions into the region of the protective circuit, and/or (2) forming a photoresist film over the region of the protective circuit to prevent ion implantation of the first ions into the protective circuit region. As a further embodiment of the present invention, a semiconductor integrated circuit device is provided wherein the source and drain regions of an MOSFET in the internal circuit have lightly doped drain (LDD) structure in order to suppress the appearance of hot carriers, and the source and drain regions of an MOSFET in the input/output circuit have structure doped with phosphorus at a high impurity concentration, in order to enhance an electrostatic breakdown voltage.

    摘要翻译： 公开了具有被静电保护电路保护的内部电路的半导体器件，内部电路和静电保护电路形成在同一半导体衬底上。 内部电路包括MIS元件，并具有双扩散漏极结构，而保护电路具有单扩散漏极结构。 内部电路可以是例如DRAM，并且保护电路可以具有扩散电阻器和钳位MIS元件。 单扩散漏极结构可以形成在半导体衬底上的保护电路中，同时通过以下步骤在同一衬底上的内部电路中提供双扩散漏极结构：（1）扫描离子注入装置以避免离子注入 第一离子进入保护电路的区域，和/或（2）在保护电路的区域上形成光致抗蚀剂膜，以防止第一离子离子注入保护电路区域。 作为本发明的另一实施例，提供了一种半导体集成电路器件，其中内部电路中的MOSFET的源极和漏极区域具有轻掺杂漏极（LDD）结构，以便抑制热载流子的出现，源极 并且输入/输出电路中的MOSFET的漏极区域掺杂有高杂质浓度的磷的结构，以增强静电击穿电压。

    Method of producing semiconductor memory device
    17.
    发明授权
    Method of producing semiconductor memory device 失效
    半导体存储器件的制造方法

    公开(公告)号：US5286666A

    公开(公告)日：1994-02-15

    申请号：US843599

    申请日：1992-02-28

    申请人： Hisao Katto ,  Jun Sugiura

    发明人： Hisao Katto ,  Jun Sugiura

    IPC分类号： H01L21/74 ,  H01L21/762 ,  H01L27/105 ,  H01L27/108 ,  H01L21/70

    CPC分类号： H01L21/76218 ,  H01L21/74 ,  H01L27/10805 ,  H01L27/105 ,  Y10S438/953

    摘要： A heavily-doped semiconductor region and a channel stopper region, which are disposed under a memory cell in a memory cell region, are simultaneously formed after formation of a field insulator film, thereby preventing the channel stopper region from oozing out into the channel region, and thus obtaining a semiconductor memory device which is resistant to .alpha.-rays and therefore free from soft errors caused by .alpha.-rays. Also disclosed is a method of producing said semiconductor memory device.

    摘要翻译： 在形成场绝缘膜之后，同时形成设置在存储单元区域中的存储单元下方的重掺杂半导体区域和沟道截止区域，从而防止沟道阻挡区域渗入沟道区域， 从而获得耐受（α）射线并因此没有由（α）射线引起的软错误的半导体存储器件。 还公开了一种制造所述半导体存储器件的方法。

    Semiconductor device and manufacturing method thereof
    18.
    发明授权
    Semiconductor device and manufacturing method thereof 失效
    半导体器件及其制造方法

    公开(公告)号：US4818716A

    公开(公告)日：1989-04-04

    申请号：US111690

    申请日：1987-10-22

    申请人： Kousuke Okuyama ,  Ken Uchida ,  Kouichi Kusuyama ,  Satoshi Meguro ,  Hisao Katto ,  Kazuhiro Komori

    发明人： Kousuke Okuyama ,  Ken Uchida ,  Kouichi Kusuyama ,  Satoshi Meguro ,  Hisao Katto ,  Kazuhiro Komori

    IPC分类号： H01L27/112 ,  H01L21/8246 ,  H01L21/265 ,  B01J17/00

    CPC分类号： H01L27/1126

    摘要： Disclosed are memory cells of a vertical-type read only memory (ROM) having a plurality of MISFETs connected in series. The MISFETs include gate electrodes formed with multiple conductive layers, in which some of the MISFETs are set to the depletion type and at least some of the remaining MISFETs are set to the enhancement type, so as to write information in the memory cells. The information write operation is conducted through at least two steps. Namely, in the first information write step, gate electrodes are used as a mask to implant an impurity; and in the second step, an impurity is implanted through the gate electrodes into the surface of the semiconductor substrate. These steps enable a semiconductor memory device, such as a vertical-type mask ROM having memory cells with a reduced series resistance and being suitable for a high degree of integration, to be produced.Furthermore, there is disclosed a memory structure of a semiconductor memory device suitable for a higher degree of integration through an arrangement of gate electrodes of multiple layers.

    摘要翻译： 公开了具有串联连接的多个MISFET的垂直型只读存储器（ROM）的存储单元。 MISFET包括形成有多个导电层的栅电极，其中一些MISFET被设置为耗尽型，并且至少一些剩余的MISFET被设置为增强型，以便将信息写入存储单元。 信息写入操作通过至少两个步骤进行。 也就是说，在第一信息写入步骤中，使用栅电极作为掩模来注入杂质; 并且在第二步骤中，通过栅电极将杂质注入到半导体衬底的表面中。 这些步骤使得能够生产半导体存储器件，例如具有降低的串联电阻并且适于高度集成的存储单元的垂直型掩模ROM。 此外，公开了一种半导体存储器件的存储结构，其适用于通过多层栅电极的布置而具有更高的集成度。