公开(公告)号：US11699499B2

公开(公告)日：2023-07-11

申请号：US17187705

申请日：2021-02-26

Applicant: KIOXIA CORPORATION

Inventor： Tsukasa Tokutomi ,  Kiwamu Watanabe ,  Riki Suzuki ,  Toshikatsu Hida ,  Takahiro Onagi

IPC: G11C29/42 ,  G11C29/24 ,  G11C29/44 ,  G11C29/12

CPC classification number: G11C29/42 ,  G11C29/24 ,  G11C29/44 ,  G11C2029/1202

Abstract: According to one embodiment, a memory system includes a memory controller and a nonvolatile memory with multiple planes each provided with multiple word lines, memory cell groups, dummy word lines, and dummy memory cell groups. The memory controller writes data to a memory cell group connected to a corresponding word line of any of the planes, such that a plane to which k-th data are to be written is different from a plane to which (k+m−1)-th data are to be written, and writes the parities to any of the dummy memory cell groups. The combinations of the data used for generating the different parities are different from each other.

公开(公告)号：US11657875B2

公开(公告)日：2023-05-23

申请号：US17849062

申请日：2022-06-24

Applicant: KIOXIA CORPORATION

Inventor： Suguru Nishikawa ,  Yoshihisa Kojima ,  Riki Suzuki ,  Masanobu Shirakawa ,  Toshikatsu Hida

IPC: G06F12/00 ,  G11C16/10 ,  G11C16/04 ,  G11C16/14 ,  G06F3/06 ,  G11C11/56 ,  G11C16/08 ,  G11C16/34 ,  G11C29/02 ,  G11C29/42 ,  G11C16/32 ,  H01L27/1157 ,  H01L27/11582

CPC classification number: G11C16/10 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0679 ,  G11C11/5628 ,  G11C11/5635 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/14 ,  G11C16/32 ,  G11C16/349 ,  G11C16/3459 ,  G11C16/3495 ,  G11C29/021 ,  G11C29/028 ,  G11C29/42 ,  G11C11/5671 ,  H01L27/1157 ,  H01L27/11582

Abstract: According to one embodiment, a memory system includes a nonvolatile semiconductor memory, and a controller. The semiconductor memory includes a memory cell, and a write circuit configured to write data to the memory cell by applying a program voltage to the memory cell and comparing a threshold voltage of the memory cell with a first reference voltage corresponding to the write data. The write circuit is configured to execute a first programming operation to obtain a value of a write parameter by comparing the threshold voltage with a second reference voltage different from the first reference voltage.

公开(公告)号：US11573740B2

公开(公告)日：2023-02-07

申请号：US17382253

申请日：2021-07-21

Applicant: KIOXIA CORPORATION

Inventor： Marie Sia ,  Yoshihisa Kojima ,  Suguru Nishikawa ,  Riki Suzuki

IPC: G06F3/06 ,  G11C11/56 ,  G11C16/04 ,  G11C16/26

Abstract: A memory system includes a non-volatile memory chip that includes a memory cell array, and a memory controller. The memory controller is configured to perform a read operation on the non-volatile memory chip by instructing the non-volatile memory chip to perform a sensing operation to read data stored in the memory cell array, estimating a time when the read data becomes ready to be transferred from the non-volatile memory chip to the memory controller, and instructing the non-volatile memory chip, after the estimated time, to perform a transfer operation to transfer the read data to the memory controller.

公开(公告)号：US11869596B2

公开(公告)日：2024-01-09

申请号：US18117520

申请日：2023-03-06

Applicant: Kioxia Corporation

Inventor： Suguru Nishikawa ,  Yoshihisa Kojima ,  Riki Suzuki ,  Masanobu Shirakawa ,  Toshikatsu Hida

IPC: G06F12/00 ,  G11C16/10 ,  G11C16/04 ,  G11C16/14 ,  G06F3/06 ,  G11C11/56 ,  G11C16/08 ,  G11C16/34 ,  G11C29/02 ,  G11C29/42 ,  G11C16/32 ,  H10B43/27 ,  H10B43/35

CPC classification number: G11C16/10 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0679 ,  G11C11/5628 ,  G11C11/5635 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/14 ,  G11C16/32 ,  G11C16/349 ,  G11C16/3459 ,  G11C16/3495 ,  G11C29/021 ,  G11C29/028 ,  G11C29/42 ,  G11C11/5671 ,  H10B43/27 ,  H10B43/35

Abstract: According to one embodiment, a memory system includes a nonvolatile semiconductor memory, and a controller. The semiconductor memory includes a memory cell, and a write circuit configured to write data to the memory cell by applying a program voltage to the memory cell and comparing a threshold voltage of the memory cell with a first reference voltage corresponding to the write data. The write circuit is configured to execute a first programming operation to obtain a value of a write parameter by comparing the threshold voltage with a second reference voltage different from the first reference voltage.

公开(公告)号：US11790993B2

公开(公告)日：2023-10-17

申请号：US18075601

申请日：2022-12-06

Applicant: KIOXIA CORPORATION

Inventor： Riki Suzuki ,  Yoshihisa Kojima

IPC: G11C16/10 ,  G11C16/26 ,  G11C16/08 ,  G11C29/44 ,  G11C16/22 ,  G11C7/10 ,  G11C29/42 ,  G11C16/30

CPC classification number: G11C16/10 ,  G11C7/1045 ,  G11C16/08 ,  G11C16/22 ,  G11C16/26 ,  G11C16/30 ,  G11C29/42 ,  G11C29/44

Abstract: A memory system includes a non-volatile memory having a plurality of memory cells and a controller. The controller is configured to switch a mode for controlling an access operation to the non-volatile memory from a first mode to a second mode, in response to receiving from a host, a first command for instructing the controller to switch the mode from the first mode to the second mode. The access operation controlled according to the second mode improves data retention relative to the access operation controlled according to the first mode.

公开(公告)号：US11696441B2

公开(公告)日：2023-07-04

申请号：US17725638

申请日：2022-04-21

Applicant: Kioxia Corporation

Inventor： Takehiko Amaki ,  Yoshihisa Kojima ,  Toshikatsu Hida ,  Marie Grace Izabelle Angeles Sia ,  Riki Suzuki ,  Shohei Asami

IPC: G11C16/08 ,  H10B41/27 ,  G11C16/10 ,  G11C16/04 ,  G11C16/16 ,  G11C7/04 ,  G11C16/26 ,  H10B43/27 ,  H10B43/35

CPC classification number: H10B41/27 ,  G11C7/04 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/107 ,  G11C16/16 ,  G11C16/26 ,  H10B43/27 ,  H10B43/35

Abstract: According to one embodiment, a memory system includes a semiconductor memory and a controller. The semiconductor memory includes blocks each containing memory cells. The controller is configured to instruct the semiconductor memory to execute a first operation and a second operation. In the first operation and the second operation, the semiconductor memory selects at least one of the blocks, and applies at least one voltage to all memory cells contained in said selected blocks. A number of blocks to which said voltage is applied per unit time in the second operation is larger than that in the first operation.

公开(公告)号：US11462256B2

公开(公告)日：2022-10-04

申请号：US17349248

申请日：2021-06-16

Applicant: Kioxia Corporation

Inventor： Shohei Asami ,  Toshikatsu Hida ,  Riki Suzuki

IPC: G11C11/40 ,  G11C11/406 ,  G11C16/16 ,  G11C16/10 ,  G11C16/34

Abstract: According to one embodiment, a memory system includes a non-volatile memory and a memory controller. The non-volatile memory includes a plurality of groups, each including a plurality of memory cells. The memory controller is configured to determine whether to execute a refresh process for a first group based on whether a first temperature in a write process for the first group and a second temperature after the write process for the first group satisfy a first condition.

公开(公告)号：US11069413B2

公开(公告)日：2021-07-20

申请号：US16799885

申请日：2020-02-25

Applicant: Kioxia Corporation

Inventor： Suguru Nishikawa ,  Riki Suzuki ,  Yoshihisa Kojima

IPC: G11C16/16 ,  G11C16/26 ,  G06F13/16 ,  G11C16/34 ,  G11C16/12

Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a memory controller that controls operation of the nonvolatile memory. The nonvolatile memory is configured to receive, from the memory controller, a first command for execution of at least one of an erase operation and a program operation; in response to receiving a second command from the memory controller during execution of a first operation requested by the first command, execute a second operation for suspending the first operation before the first operation reaches a given section; and in response to receiving a third command from the memory controller during the execution of the first operation, suspend the first operation after the given section.

公开(公告)号：US12086439B2

公开(公告)日：2024-09-10

申请号：US18343835

申请日：2023-06-29

Applicant: KIOXIA CORPORATION

Inventor： Shunichi Igahara ,  Toshikatsu Hida ,  Riki Suzuki ,  Takehiko Amaki ,  Suguru Nishikawa ,  Yoshihisa Kojima

IPC: G06F3/06 ,  G06F12/02 ,  G06F12/10

CPC classification number: G06F3/0634 ,  G06F3/0604 ,  G06F3/061 ,  G06F3/0619 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/0253 ,  G06F12/10 ,  G06F2212/1044 ,  G06F2212/657

Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller electrically connected to the nonvolatile memory. The controller selects a write mode from a first mode in which data having N bits is written per one memory cell and a second mode in which data having M bits is written per one memory cell. N is equal to or larger than one. M is larger than N. The controller writes data into the nonvolatile memory in the selected write mode. The controller selects either the first mode or the second mode at least based on a total number of logical addresses mapped in a physical address space of the nonvolatile memory.

公开(公告)号：US11733888B2

公开(公告)日：2023-08-22

申请号：US17028087

申请日：2020-09-22

Applicant: Kioxia Corporation

Inventor： Shunichi Igahara ,  Toshikatsu Hida ,  Riki Suzuki ,  Takehiko Amaki ,  Suguru Nishikawa ,  Yoshihisa Kojima

IPC: G06F3/06 ,  G06F12/10 ,  G06F12/02

CPC classification number: G06F3/0634 ,  G06F3/061 ,  G06F3/0604 ,  G06F3/0619 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/0253 ,  G06F12/10 ,  G06F2212/1044 ,  G06F2212/657

Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller electrically connected to the nonvolatile memory. The controller selects a write mode from a first mode in which data having N bits is written per one memory cell and a second mode in which data having M bits is written per one memory cell. N is equal to or larger than one. M is larger than N. The controller writes data into the nonvolatile memory in the selected write mode. The controller selects either the first mode or the second mode at least based on a total number of logical addresses mapped in a physical address space of the nonvolatile memory.