公开(公告)号：US20170338183A1

公开(公告)日：2017-11-23

申请号：US15672440

申请日：2017-08-09

Applicant: MEDIATEK Inc.

Inventor： Wen-Sung Hsu ,  Shih-Chin Lin ,  Tao Cheng ,  Andrew C. Chang

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L23/14 ,  H01L23/498 ,  H01L23/50 ,  H01L25/065 ,  H01L25/10 ,  H01L25/00 ,  H01L25/16 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L23/5389 ,  H01L21/4846 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/565 ,  H01L21/568 ,  H01L23/145 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/50 ,  H01L24/13 ,  H01L24/16 ,  H01L24/48 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/10 ,  H01L25/105 ,  H01L25/16 ,  H01L25/162 ,  H01L25/165 ,  H01L25/50 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/48227 ,  H01L2224/81005 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/1533 ,  H01L2924/1579 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19106 ,  H01L2924/014 ,  H01L2224/45099

Abstract: A manufacturing method of a semiconductor package includes the follow steps. Firstly, a carrier is provided. Then, a package substrate is formed. Then, a first electronic component is disposed above the second conductive layer of the package substrate. Then, a second package body encapsulating the first electronic component and the second conductive layer is formed. Then, the carrier is carried. Wherein in the step of forming the package substrate includes a step of forming a first conductive layer on the carrier, a step of forming a first pillar layer on the first conductive layer, a step of forming a first package body encapsulating the first conductive layer and the first pillar layer and a step of forming a second conductive layer on the first pillar layer.

公开(公告)号：US20170136582A1

公开(公告)日：2017-05-18

申请号：US15420140

申请日：2017-01-31

Applicant: MEDIATEK Inc.

Inventor： Tao Cheng ,  Wen-Sung Hsu ,  Shih-Chin Lin

IPC: B23K35/02 ,  H01L25/10 ,  B23K35/26 ,  H01L23/498

CPC classification number: B23K35/0244 ,  B23K35/26 ,  B23K35/262 ,  B23K35/264 ,  B23K35/30 ,  B23K2101/40 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/49866 ,  H01L23/49894 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L25/105 ,  H01L2224/13014 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13561 ,  H01L2224/13582 ,  H01L2224/13611 ,  H01L2224/13639 ,  H01L2224/13647 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81801 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/014 ,  H01L2924/1434 ,  H01L2924/15331 ,  H01L2924/2076 ,  H01L2924/00

Abstract: A semiconductor package includes a first substrate, a second substrate, a composite solder ball and a first semiconductor component. The composite solder ball includes a core, an encapsulating layer and a barrier layer. The composite solder ball is disposed between the first substrate and the second substrate for electrically connecting the first substrate and the second substrate. The barrier layer is disposed between the core and the encapsulating layer. Wherein a melting point of the barrier layer is higher than a melting point of the core, the melting point of the core is higher than a melting point of the encapsulating layer. The first semiconductor component is disposed between the first substrate and the second substrate.

公开(公告)号：US09597752B2

公开(公告)日：2017-03-21

申请号：US14918698

申请日：2015-10-21

Applicant: MEDIATEK Inc.

Inventor： Tao Cheng ,  Wen-Sung Hsu ,  Shih-Chin Lin

IPC: H01L23/48 ,  B23K35/02 ,  H01L23/00 ,  B23K35/26 ,  B23K35/30 ,  H01L23/498

CPC classification number: B23K35/0244 ,  B23K35/26 ,  B23K35/262 ,  B23K35/264 ,  B23K35/30 ,  B23K2101/40 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/49866 ,  H01L23/49894 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L25/105 ,  H01L2224/13014 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13561 ,  H01L2224/13582 ,  H01L2224/13611 ,  H01L2224/13639 ,  H01L2224/13647 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81801 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/014 ,  H01L2924/1434 ,  H01L2924/15331 ,  H01L2924/2076 ,  H01L2924/00

Abstract: A semiconductor package includes a first substrate, a second substrate, a composite solder ball and a first semiconductor component. The composite solder ball includes a core, an encapsulating layer and a barrier layer. The composite solder ball is disposed between the first substrate and the second substrate for electrically connecting the first substrate and the second substrate. The barrier layer is disposed between the core and the encapsulating layer. Wherein a melting point of the barrier layer is higher than a melting point of the core, the melting point of the core is higher than a melting point of the encapsulating layer. The first semiconductor component is disposed between the first substrate and the second substrate.

公开(公告)号：US11373957B2

公开(公告)日：2022-06-28

申请号：US16994764

申请日：2020-08-17

Applicant: MEDIATEK Inc.

Inventor： Wen-Sung Hsu ,  Tao Cheng ,  Nan-Cheng Chen ,  Che-Ya Chou ,  Wen-Chou Wu ,  Yen-Ju Lu ,  Chih-Ming Hung ,  Wei-Hsiu Hsu

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/31 ,  H01L23/498 ,  H01L23/50 ,  H01L23/66 ,  H01L25/065 ,  H01L25/10 ,  H01L25/16 ,  H01L25/00 ,  H01Q1/22 ,  H01Q9/04 ,  H01L23/14 ,  H01L23/00 ,  H01Q21/06

Abstract: A semiconductor package includes a first substrate, a first layer structure, a second layer structure, a first antenna layer and an electronic component. The first antenna layer is formed on at least one of the first layer structure and the second layer structure, wherein the first antenna layer has an upper surface flush with a layer upper surface of the first layer structure or the second layer structure. The electronic component is disposed on a substrate lower surface of the first substrate and exposed from the first substrate. The first layer structure is formed between the first substrate and the second layer structure.

公开(公告)号：US09881902B2

公开(公告)日：2018-01-30

申请号：US15162724

申请日：2016-05-24

Applicant: MEDIATEK Inc.

Inventor： Wen-Sung Hsu ,  Shih-Chin Lin ,  Tao Cheng

IPC: H01L25/16 ,  H01L25/065 ,  H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/538 ,  H01L25/10 ,  H01L25/00 ,  H01L21/52

CPC classification number: H01L25/0657 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/52 ,  H01L21/568 ,  H01L23/49805 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/5389 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/48235 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06572 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043

Abstract: A semiconductor package includes a substrate, a first electronic component, a first conductive layer, a first pillar layer and a first package body. The first electronic component is disposed on the substrate. The first pillar layer connects the first conductive layer and the substrate. The first package body encapsulates the first conductive layer, the first pillar layer and the first electronic component. The first conductive layer is embedded in the first package body.

公开(公告)号：US20170263559A1

公开(公告)日：2017-09-14

申请号：US15604924

申请日：2017-05-25

Applicant: MediaTek Inc.

Inventor： Ching-Chung Ko ,  Tao Cheng ,  Tien-Yueh Liu ,  Ta-Hsi Chou ,  Peng-Cheng Kao ,  Ling-Wei Ke

IPC: H01L23/528 ,  H01L23/00 ,  H01L23/532 ,  H01L23/58 ,  H01L21/8234 ,  H01L23/522

CPC classification number: H01L23/5286 ,  H01L21/823475 ,  H01L23/5226 ,  H01L23/53228 ,  H01L23/585 ,  H01L24/05 ,  H01L2224/05124 ,  H01L2924/0002 ,  H01L2924/14 ,  H01L2924/00

Abstract: An integrated circuit chip includes a semiconductor substrate having thereon a plurality of inter-metal dielectric (IMD) layers and a plurality of first conductive layers embedded in respective said plurality of IMD layers, wherein said first conductive layers comprise copper; a first insulating layer overlying said plurality of IMD layers and said plurality of first conductive layers; at least a first wiring line in a second conductive layer overlying said first insulating layer, for distributing power signal or ground signal, wherein said second conductive layer comprise aluminum; and at least a second wiring line in a third conductive layer overlying said second conductive layer, for distributing power signal or ground signal.

公开(公告)号：US20170084541A1

公开(公告)日：2017-03-23

申请号：US15162760

申请日：2016-05-24

Applicant: MEDIATEK Inc.

Inventor： Wen-Sung Hsu ,  Shih-Chin Lin ,  Tao Cheng ,  Andrew C. Chang

IPC: H01L23/538 ,  H01L21/56 ,  H01L25/00 ,  H01L21/48 ,  H01L23/31 ,  H01L25/10

CPC classification number: H01L23/5389 ,  H01L21/4846 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/565 ,  H01L21/568 ,  H01L23/145 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/50 ,  H01L24/13 ,  H01L24/16 ,  H01L24/48 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/10 ,  H01L25/105 ,  H01L25/16 ,  H01L25/162 ,  H01L25/165 ,  H01L25/50 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/48227 ,  H01L2224/81005 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/1533 ,  H01L2924/1579 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19106 ,  H01L2924/014 ,  H01L2224/45099

Abstract: A semiconductor package includes a package substrate, a first electronic component and a second package body. The package substrate includes a first conductive layer, a first pillar layer, a first package body and a second conductive layer, wherein the first pillar layer is formed on the first conductive layer, the first package body encapsulates the first conductive layer and the first pillar layer, and the second conductive layer electrically connects to the first pillar layer. The first electronic component is disposed above the second conductive layer of the package substrate. The second package body encapsulates the first electronic component and the second conductive layer.

公开(公告)号：US20160263709A1

公开(公告)日：2016-09-15

申请号：US14918698

申请日：2015-10-21

Applicant: MEDIATEK Inc.

Inventor： Tao Cheng ,  Wen-Sung Hsu ,  Shih-Chin Lin

IPC: B23K35/02 ,  B23K35/26 ,  B23K35/30 ,  H01L23/00

CPC classification number: B23K35/0244 ,  B23K35/26 ,  B23K35/262 ,  B23K35/264 ,  B23K35/30 ,  B23K2101/40 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/49866 ,  H01L23/49894 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L25/105 ,  H01L2224/13014 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13561 ,  H01L2224/13582 ,  H01L2224/13611 ,  H01L2224/13639 ,  H01L2224/13647 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81801 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/014 ,  H01L2924/1434 ,  H01L2924/15331 ,  H01L2924/2076 ,  H01L2924/00

Abstract: A semiconductor package includes a first substrate, a second substrate, a composite solder ball and a first semiconductor component. The composite solder ball includes a core, an encapsulating layer and a barrier layer. The composite solder ball is disposed between the first substrate and the second substrate for electrically connecting the first substrate and the second substrate. The barrier layer is disposed between the core and the encapsulating layer. Wherein a melting point of the barrier layer is higher than a melting point of the core, the melting point of the core is higher than a melting point of the encapsulating layer. The first semiconductor component is disposed between the first substrate and the second substrate.

Abstract translation: 半导体封装包括第一基板，第二基板，复合焊球和第一半导体部件。 复合焊球包括芯，封装层和阻挡层。 复合焊球设置在第一基板和第二基板之间，用于电连接第一基板和第二基板。 阻挡层设置在芯和封装层之间。 其中阻挡层的熔点高于芯的熔点，芯的熔点高于封装层的熔点。 第一半导体部件设置在第一基板和第二基板之间。

公开(公告)号：US20160043040A1

公开(公告)日：2016-02-11

申请号：US14686783

申请日：2015-04-15

Applicant: MEDIATEK INC.

Inventor： Chin-Chiang Chang ,  Tao Cheng

IPC: H01L23/00 ,  H01L23/498 ,  H01L23/31

CPC classification number: H01L23/562 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/49838 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: The present invention provides an integrated circuit (IC) package with stress releasing structure. The IC package comprises: a metal plane, a substrate, an IC chip, and an IC fill layer. The metal plane has at least one first etching line for separating the metal plane into a plurality of areas. The substrate is formed on metal layer. The IC chip is formed on the substrate, and the IC fill layer is formed around the IC chip. The at least one first etching line forms at least one half cut line in the metal plane and the substrate.

Abstract translation: 本发明提供一种具有应力释放结构的集成电路（IC）封装。 IC封装包括：金属平面，基板，IC芯片和IC填充层。 金属平面具有用于将金属平面分离成多个区域的至少一个第一蚀刻线。 衬底形成在金属层上。 IC芯片形成在基板上，IC填充层围绕IC芯片形成。 所述至少一个第一蚀刻线在所述金属平面和所述基板中形成至少一条半切割线。

公开(公告)号：US20150001675A1

公开(公告)日：2015-01-01

申请号：US14490690

申请日：2014-09-19

Applicant: MEDIATEK INC.

Inventor： Tien-Chang Chang ,  Ming-Tzong Yang ,  Tao Cheng ,  Cheng-Hsing Chien ,  Hsin-Hsin Hsiao

IPC: H01L49/02 ,  H01L27/06

CPC classification number: H01L28/40 ,  H01L27/0629 ,  H01L27/0811 ,  H01L29/94

Abstract: A semiconductor circuit comprises a first and a second logic circuit, a first and a second decoupling capacitor. The first decoupling capacitor is arranged in a first area around the first logic circuit and the second decoupling capacitor is arranged in a second area around the second logic circuit. Wherein, the first area is larger than the second area, a gate oxide thickness of the first decoupling capacitor is larger than a gate oxide thickness of the second decoupling capacitor, and a distance between the first area and the first logic circuit is shorter than a distance between the second area and the second logic circuit. Further, the first and second decoupling capacitors are designed without trench.

Abstract translation: 半导体电路包括第一和第二逻辑电路，第一和第二去耦电容器。 第一去耦电容器布置在第一逻辑电路周围的第一区域中，并且第二去耦电容器布置在第二逻辑电路周围的第二区域中。 其中，第一区域大于第二区域，第一去耦电容器的栅极氧化物厚度大于第二去耦电容器的栅极氧化物厚度，并且第一区域和第一逻辑电路之间的距离短于第 第二区域与第二逻辑电路之间的距离。 此外，第一和第二去耦电容器被设计成没有沟槽。