公开(公告)号：US20150348956A1

公开(公告)日：2015-12-03

申请号：US14825009

申请日：2015-08-12

Applicant: Micron Technology, Inc.

Inventor： Steven K. Groothuis ,  Jian Li ,  Haojun Zhang ,  Paul A. Silvestri ,  Xiao Li ,  Shijan Luo ,  Luke G. England ,  Brent Keeth ,  Jaspreet S. Gandhi

IPC: H01L25/00 ,  H01L23/367 ,  H01L25/065

CPC classification number: H01L23/36 ,  H01L23/3675 ,  H01L23/3677 ,  H01L23/3736 ,  H01L23/42 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2225/06589 ,  H01L2924/15311

Abstract: Stacked semiconductor die assemblies with multiple thermal paths and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a plurality of first semiconductor dies arranged in a stack and a second semiconductor die carrying the first semiconductor dies. The second semiconductor die can include a peripheral portion that extends laterally outward beyond at least one side of the first semiconductor dies. The semiconductor die assembly can further include a thermal transfer feature at the peripheral portion of the second semiconductor die. The first semiconductor dies can define a first thermal path, and the thermal transfer feature can define a second thermal path separate from the first semiconductor dies.

Abstract translation: 本文公开了具有多个热路径和相关系统和方法的堆叠的半导体管芯组件。 在一个实施例中，半导体管芯组件可以包括布置在堆叠中的多个第一半导体管芯和承载第一半导体管芯的第二半导体管芯。 第二半导体管芯可以包括横向向外延伸超过第一半导体管芯的至少一侧的周边部分。 半导体管芯组件还可以包括在第二半导体管芯的周边部分处的热传递特征。 第一半导体管芯可以限定第一热路径，并且热转移特征可以限定与第一半导体管芯分离的第二热路径。

公开(公告)号：US10170389B2

公开(公告)日：2019-01-01

申请号：US14825009

申请日：2015-08-12

Applicant: Micron Technology, Inc.

Inventor： Steven K. Groothuis ,  Jian Li ,  Haojun Zhang ,  Paul A. Silvestri ,  Xiao Li ,  Shijian Luo ,  Luke G. England ,  Brent Keeth ,  Jaspreet S. Gandhi

IPC: H01L21/00 ,  H01L23/495 ,  H01L23/10 ,  H01L23/34 ,  H01L23/48 ,  H01L23/52 ,  H01L23/36 ,  H01L25/00 ,  H01L23/367 ,  H01L23/373 ,  H01L23/42 ,  H01L25/065 ,  H01L25/18

Abstract: Stacked semiconductor die assemblies with multiple thermal paths and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a plurality of first semiconductor dies arranged in a stack and a second semiconductor die carrying the first semiconductor dies. The second semiconductor die can include a peripheral portion that extends laterally outward beyond at least one side of the first semiconductor dies. The semiconductor die assembly can further include a thermal transfer feature at the peripheral portion of the second semiconductor die. The first semiconductor dies can define a first thermal path, and the thermal transfer feature can define a second thermal path separate from the first semiconductor dies.

公开(公告)号：US20150132869A1

公开(公告)日：2015-05-14

申请号：US14600976

申请日：2015-01-20

Applicant: Micron Technology, Inc.

Inventor： Luke G. England ,  Paul A. Silvestri ,  Michel Koopmans

IPC: H01L25/00 ,  H01L21/66 ,  H01L23/00 ,  H01L21/56 ,  H01L21/78

CPC classification number: H01L25/50 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/78 ,  H01L22/14 ,  H01L22/20 ,  H01L22/32 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/544 ,  H01L24/89 ,  H01L24/96 ,  H01L25/0657 ,  H01L25/18 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2223/54433 ,  H01L2224/16145 ,  H01L2224/80203 ,  H01L2224/80815 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06596 ,  H01L2924/12042 ,  H01L2924/00

Abstract: Methods of fabricating multi-die assemblies including a base semiconductor die bearing a peripherally encapsulated stack of semiconductor dice of lesser lateral dimensions, the dice vertically connected by conductive elements between the dice, resulting assemblies, and semiconductor devices comprising such assemblies.

Abstract translation: 制造多模组件的方法，其包括具有较小横向尺寸的半导体芯片的外围封装的叠层的基底半导体模具，所述芯片由芯片，所得组件和包括这种组件的半导体器件之间的导电元件垂直连接。

公开(公告)号：US20140167259A1

公开(公告)日：2014-06-19

申请号：US14186869

申请日：2014-02-21

Applicant: Micron Technology, Inc.

Inventor： Owen R. Fay ,  Luke G. England ,  Christopher J. Gambee

IPC: H01L23/00

CPC classification number: H01L24/14 ,  H01L21/0274 ,  H01L21/311 ,  H01L21/56 ,  H01L23/291 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/83 ,  H01L24/94 ,  H01L25/0657 ,  H01L2224/0345 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05567 ,  H01L2224/05647 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/1191 ,  H01L2224/13005 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16148 ,  H01L2224/16238 ,  H01L2224/73204 ,  H01L2224/81011 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/83104 ,  H01L2224/92125 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/35121 ,  H01L2924/365 ,  H01L2924/3651 ,  H01L2924/381 ,  H01L2924/014 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/206 ,  H01L2224/05552 ,  H01L2224/11

Abstract: Methods of fabricating interconnect structures for semiconductor dice comprise forming conductive elements in contact with bond pads on an active surface over a full pillar diameter of the conductive elements, followed by application of a photodefinable material comprising a photoresist to the active surface and over the conductive elements. The polyimide material is selectively exposed and developed to remove photodefinable material covering at least tops of the conductive elements. Semiconductor dice and semiconductor die assemblies are also disclosed.

Abstract translation: 制造用于半导体晶片的互连结构的方法包括形成与导电元件的全柱直径上的有源表面上的接合焊盘接触的导电元件，随后将包含光致抗蚀剂的可光限定材料施加到有源表面上并在导电元件上 。 聚酰亚胺材料被选择性地曝光和显影以除去覆盖至少导电元件顶部的可光限定材料。 还公开了半导体管芯和半导体管芯组件。

公开(公告)号：US11594462B2

公开(公告)日：2023-02-28

申请号：US16936639

申请日：2020-07-23

Applicant: Micron Technology, Inc.

Inventor： Steven K. Groothuis ,  Jian Li ,  Haojun Zhang ,  Paul A. Silvestri ,  Xiao Li ,  Shijian Luo ,  Luke G. England ,  Brent Keeth ,  Jaspreet S. Gandhi

IPC: H01L23/36 ,  H01L23/367 ,  H01L23/373 ,  H01L23/42 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00

Abstract: Stacked semiconductor die assemblies with multiple thermal paths and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a plurality of first semiconductor dies arranged in a stack and a second semiconductor die carrying the first semiconductor dies. The second semiconductor die can include a peripheral portion that extends laterally outward beyond at least one side of the first semiconductor dies. The semiconductor die assembly can further include a thermal transfer feature at the peripheral portion of the second semiconductor die. The first semiconductor dies can define a first thermal path, and the thermal transfer feature can define a second thermal path separate from the first semiconductor dies.

公开(公告)号：US10741468B2

公开(公告)日：2020-08-11

申请号：US16229257

申请日：2018-12-21

Applicant: Micron Technology, Inc.

Inventor： Steven K. Groothuis ,  Jian Li ,  Haojun Zhang ,  Paul A. Silvestri ,  Xiao Li ,  Shijian Luo ,  Luke G. England ,  Brent Keeth ,  Jaspreet S. Gandhi

IPC: H01L23/36 ,  H01L23/367 ,  H01L23/42 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18 ,  H01L23/373

Abstract: Stacked semiconductor die assemblies with multiple thermal paths and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a plurality of first semiconductor dies arranged in a stack and a second semiconductor die carrying the first semiconductor dies. The second semiconductor die can include a peripheral portion that extends laterally outward beyond at least one side of the first semiconductor dies. The semiconductor die assembly can further include a thermal transfer feature at the peripheral portion of the second semiconductor die. The first semiconductor dies can define a first thermal path, and the thermal transfer feature can define a second thermal path separate from the first semiconductor dies.

公开(公告)号：US10134647B2

公开(公告)日：2018-11-20

申请号：US15478133

申请日：2017-04-03

Applicant: Micron Technology, Inc.

Inventor： Owen R. Fay ,  Kyle K. Kirby ,  Luke G. England ,  Jaspreet S. Gandhi

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/66 ,  H01L23/00

Abstract: An interconnect assembly includes a bond pad and an interconnect structure configured to electrically couple an electronic structure to the bond pad. The interconnect structure physically contacts areas of the bond pad that are located outside of a probe contact area that may have been damaged during testing. Insulating material covers the probe contact area and defines openings spaced apart from the probe contact area. The interconnect structure extends through the openings to contact the bond pad.

公开(公告)号：US09711494B2

公开(公告)日：2017-07-18

申请号：US14600976

申请日：2015-01-20

Applicant: Micron Technology, Inc.

Inventor： Luke G. England ,  Paul A. Silvestri ,  Michel Koopmans

IPC: H01L21/00 ,  H01L23/00 ,  H05K1/00 ,  H01L25/00 ,  H01L21/56 ,  H01L23/544 ,  H01L25/065 ,  H01L25/18 ,  H01L21/78 ,  H01L23/31 ,  H01L21/66 ,  H01L21/683

CPC classification number: H01L25/50 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/78 ,  H01L22/14 ,  H01L22/20 ,  H01L22/32 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/544 ,  H01L24/89 ,  H01L24/96 ,  H01L25/0657 ,  H01L25/18 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2223/54433 ,  H01L2224/16145 ,  H01L2224/80203 ,  H01L2224/80815 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06596 ,  H01L2924/12042 ,  H01L2924/00

Abstract: Methods of fabricating multi-die assemblies including a base semiconductor die bearing a peripherally encapsulated stack of semiconductor dice of lesser lateral dimensions, the dice vertically connected by conductive elements between the dice, resulting assemblies, and semiconductor devices comprising such assemblies.

公开(公告)号：US09129869B2

公开(公告)日：2015-09-08

申请号：US14186869

申请日：2014-02-21

Applicant: Micron Technology, Inc.

Inventor： Owen R. Fay ,  Luke G. England ,  Christopher J. Gambee

IPC: H01L21/4763 ,  H01L23/00 ,  H01L21/027 ,  H01L21/311 ,  H01L23/29 ,  H01L23/31 ,  H01L21/56 ,  H01L25/065

CPC classification number: H01L24/14 ,  H01L21/0274 ,  H01L21/311 ,  H01L21/56 ,  H01L23/291 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/83 ,  H01L24/94 ,  H01L25/0657 ,  H01L2224/0345 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05567 ,  H01L2224/05647 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/1191 ,  H01L2224/13005 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16148 ,  H01L2224/16238 ,  H01L2224/73204 ,  H01L2224/81011 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/83104 ,  H01L2224/92125 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/35121 ,  H01L2924/365 ,  H01L2924/3651 ,  H01L2924/381 ,  H01L2924/014 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/206 ,  H01L2224/05552 ,  H01L2224/11

Abstract: Methods of fabricating interconnect structures for semiconductor dice comprise forming conductive elements in contact with bond pads on an active surface over a full pillar diameter of the conductive elements, followed by application of a photodefinable material comprising a photoresist to the active surface and over the conductive elements. The polyimide material is selectively exposed and developed to remove photodefinable material covering at least tops of the conductive elements. Semiconductor dice and semiconductor die assemblies are also disclosed.

Abstract translation: 制造用于半导体晶片的互连结构的方法包括形成与导电元件的全柱直径上的有源表面上的接合焊盘接触的导电元件，随后将包含光致抗蚀剂的可光限定材料施加到有源表面上并在导电元件上 。 聚酰亚胺材料被选择性地曝光和显影以除去覆盖至少导电元件顶部的可光限定材料。 还公开了半导体管芯和半导体管芯组件。

公开(公告)号：US08828798B2

公开(公告)日：2014-09-09

申请号：US14029187

申请日：2013-09-17

Applicant: Micron Technology, Inc.

Inventor： Luke G. England ,  Paul A. Silvestri ,  Michel Koopmans

IPC: H01L21/50 ,  H01L21/48 ,  H01L21/66 ,  H01L21/44 ,  H01L23/00 ,  H01L21/56 ,  H01L25/00 ,  H01L25/065 ,  H01L21/683 ,  H01L25/18 ,  H01L23/31

CPC classification number: H01L25/0657 ,  H01L21/56 ,  H01L21/561 ,  H01L21/6836 ,  H01L22/10 ,  H01L22/32 ,  H01L23/3128 ,  H01L23/367 ,  H01L23/481 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L24/94 ,  H01L24/97 ,  H01L25/18 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2224/0401 ,  H01L2224/05655 ,  H01L2224/11332 ,  H01L2224/11334 ,  H01L2224/11849 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2224/11 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2924/00

Abstract: Methods of fabricating multi-die assemblies including a wafer segment having no integrated circuitry thereon and having a plurality of vertically stacked dice thereon electrically interconnected by conductive through vias, resulting multi-die assemblies, and semiconductor devices comprising such multi-die assemblies. The wafer segment may function as a heat sink to enhance heat transfer from the stacked dice in the resulting multi-die assembly. The die stacks are fabricated at the wafer level on a base wafer, from which the wafer segment and die stacks are singulated after at least peripheral encapsulation.

Abstract translation: 制造多模组件的方法，其包括在其上没有集成电路并且具有多个垂直堆叠的骰子的晶片片段，其上通过导电通孔，所得到的多骰子组件和包括这种多模组件的半导体器件电连接。 晶片段可用作散热器，以增强在所得到的多模组件中从堆叠的骰子的热传递。 芯片堆叠在基底晶片上的晶片级制造，晶片段和管芯堆叠至少在至少外围封装之后被分割。