公开(公告)号：US20150074346A1

公开(公告)日：2015-03-12

申请号：US14324228

申请日：2014-07-06

Applicant: MEDIATEK INC.

Inventor： Yan-Bin Luo ,  Sheng-Ming Chang ,  Bo-Wei Hsieh ,  Ming-Shi Liou ,  Chih-Chien Hung ,  Shang-Pin Chen

IPC: G11C7/10 ,  G11C8/12

CPC classification number: G11C8/12 ,  G06F12/00 ,  G06F13/1668

Abstract: A memory module, comprising: a first pin, arranged to receive a first signal; a second pin, arranged to receive second signal; a first conducting path, having a first end coupled to the first pin; at least one memory chip, coupled to the first conducting path for receiving the first signal; a predetermined resistor, having a first terminal coupled to a second end of the first conducting path; and a second conducting path, having a first end coupled to second pin for conducting the second to a second terminal of the predetermined resistor; wherein the first signal and the second are synchronous and configured to be a differential signal, for enabling a selected memory chip from the at least one memory chip to be accessed.

Abstract translation: 一种存储器模块，包括：第一引脚，布置成接收第一信号; 布置成接收第二信号的第二引脚; 第一导电路径，其具有耦合到第一引脚的第一端; 至少一个存储器芯片，耦合到所述第一导电路径，用于接收所述第一信号; 预定的电阻器，具有耦合到第一导电路径的第二端的第一端子; 以及第二导电路径，其具有耦合到第二引脚的第一端，用于将第二端子传导到预定电阻器的第二端子; 其中所述第一信号和所述第二信号是同步的并且被配置为差分信号，用于使来自所述至少一个存储器芯片的所选择的存储器芯片被访问。

公开(公告)号：US11573264B2

公开(公告)日：2023-02-07

申请号：US16828925

申请日：2020-03-24

Applicant: MEDIATEK INC.

Inventor： Ching-Chih Li ,  Sheng-Ming Chang

IPC: G01R31/28

Abstract: The present invention provides a device for testing a chip, wherein the device includes a testing board and an interposer. The testing board has a plurality of pads for providing a plurality of test signals. The interposer board includes a plurality of passive components, and at least one of the passive components is coupled between a supply voltage and a ground voltage, and the supply voltage and the ground voltage are received from a power pad and a ground pad of the plurality of pads of the testing board, respectively; wherein the chip is positioned in the device, the chip receives the test signals including the supply voltage and the ground voltage from the power pad and the ground pad of the testing board, respectively.

公开(公告)号：US09883591B2

公开(公告)日：2018-01-30

申请号：US15431781

申请日：2017-02-14

Applicant: MEDIATEK INC.

Inventor： Sheng-Ming Chang ,  Chia-Hui Liu ,  Shih-Chieh Lin ,  Chun-Ping Chen

IPC: H05K1/11 ,  H01L23/00 ,  H01L23/498 ,  H05K1/18 ,  H05K1/05

CPC classification number: H05K1/115 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/50 ,  H01L24/16 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K1/0262 ,  H05K1/0298 ,  H05K1/05 ,  H05K1/111 ,  H05K1/114 ,  H05K1/181 ,  H05K2201/09227 ,  H05K2201/095 ,  H05K2201/09509 ,  H05K2201/10378 ,  H05K2201/10674 ,  H05K2201/10734 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A microelectronic system includes a printed circuit board and a semiconductor package mounted on the printed circuit board. The printed circuit board includes a laminated core having an internal conductive layer and a build-up layer. The build-up layer includes a top conductive layer. Microvias are disposed in the build-up layer to connect the top conductive layer with the internal conductive layer. A power/ground ball pad array is disposed in the top conductive layer. The power/ground ball pad array includes power ball pads and ground ball pads arranged in an array with a fixed ball pad pitch P. The power/ground ball pad array includes a 4-ball pad unit area comprised of only one ground ball pad and three power ball pads, or comprised of only one power ball pad and three ground ball pads. The 4-ball pad unit area has a rectangular shape and a dimension of about 2P×2P.

公开(公告)号：US09674941B2

公开(公告)日：2017-06-06

申请号：US14816204

申请日：2015-08-03

Applicant: MediaTek Inc.

Inventor： Sheng-Ming Chang ,  Shih-Chieh Lin ,  Nan-Cheng Chen

IPC: H05K1/00 ,  H05K1/02 ,  H05K1/11

CPC classification number: H05K1/0219 ,  H05K1/0218 ,  H05K1/025 ,  H05K1/0298 ,  H05K1/114 ,  H05K1/115 ,  H05K2201/0723 ,  H05K2201/09672 ,  H05K2201/09709 ,  H05K2201/10522 ,  H05K2201/10674

Abstract: A printed circuit board for mobile platforms includes a core substrate having a first side, a ground plane covering on the first side, a first insulating layer covering the ground plane, and a plurality of first signal traces and a plurality of first ground traces, alternatively arranged on the first insulating layer, a second insulating layer connecting to the first insulating layer, and a plurality of second signal traces separated from each other, disposed on the second insulating layer, wherein the second signal traces are disposed directly on spaces between the first signal traces and the first ground traces adjacent thereto, wherein coverage of the ground plane is corresponding to disposition of the first signal trace, the first ground trace, the second signal trace and the second ground trace.

公开(公告)号：US20170156208A1

公开(公告)日：2017-06-01

申请号：US15431781

申请日：2017-02-14

Applicant: MEDIATEK INC.

Inventor： Sheng-Ming Chang ,  Chia-Hui Liu ,  Shih-Chieh Lin ,  Chun-Ping Chen

IPC: H05K1/11 ,  H01L23/00 ,  H01L23/498 ,  H05K1/18 ,  H05K1/05

CPC classification number: H05K1/115 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/50 ,  H01L24/16 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K1/0262 ,  H05K1/0298 ,  H05K1/05 ,  H05K1/111 ,  H05K1/114 ,  H05K1/181 ,  H05K2201/09227 ,  H05K2201/095 ,  H05K2201/09509 ,  H05K2201/10378 ,  H05K2201/10674 ,  H05K2201/10734 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A microelectronic system includes a printed circuit board and a semiconductor package mounted on the printed circuit board. The printed circuit board includes a laminated core having an internal conductive layer and a build-up layer. The build-up layer includes a top conductive layer. Microvias are disposed in the build-up layer to connect the top conductive layer with the internal conductive layer. A power/ground ball pad array is disposed in the top conductive layer. The power/ground ball pad array includes power ball pads and ground ball pads arranged in an array with a fixed ball pad pitch P. The power/ground ball pad array includes a 4-ball pad unit area comprised of only one ground ball pad and three power ball pads, or comprised of only one power ball pad and three ground ball pads. The 4-ball pad unit area has a rectangular shape and a dimension of about 2P×2P.

公开(公告)号：US09609749B2

公开(公告)日：2017-03-28

申请号：US14860718

申请日：2015-09-22

Applicant: MEDIATEK INC.

Inventor： Sheng-Ming Chang ,  Chia-Hui Liu ,  Shih-Chieh Lin ,  Chun-Ping Chen

IPC: H05K1/11 ,  H05K1/02

CPC classification number: H05K1/115 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/50 ,  H01L24/16 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K1/0262 ,  H05K1/0298 ,  H05K1/05 ,  H05K1/111 ,  H05K1/114 ,  H05K1/181 ,  H05K2201/09227 ,  H05K2201/095 ,  H05K2201/09509 ,  H05K2201/10378 ,  H05K2201/10674 ,  H05K2201/10734 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A printed circuit board includes a laminated core including at least an internal conductive layer, and a build-up layer on the laminated core. The build-up layer includes a top conductive layer. A plurality of microvias is disposed in the build-up layer to electrically connect the top conductive layer with the internal conductive layer. A power/ground ball pad array is disposed in the top conductive layer. The power/ground ball pad array includes power ball pads and ground ball pads arranged in an array with a fixed ball pad pitch P. The power/ground ball pad array includes a 4-ball pad unit area that is comprised of only one ground ball pad and three power ball pads, or comprised of only one power ball pad and three ground ball pads. The 4-ball pad unit area has a rectangular shape and a dimension of about 2P×2P.

公开(公告)号：US09331054B2

公开(公告)日：2016-05-03

申请号：US14188881

申请日：2014-02-25

Applicant: MediaTek Inc.

Inventor： Sheng-Ming Chang ,  Tung-Hsien Hsieh ,  Nan-Cheng Chen

IPC: H01L25/065 ,  H01L25/10 ,  H01L23/31 ,  H01L23/00 ,  H01L25/16 ,  H01L25/18 ,  H05K1/18

CPC classification number: H01L25/0657 ,  H01L23/3128 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/92 ,  H01L25/0655 ,  H01L25/105 ,  H01L25/16 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/06135 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/49433 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/92125 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/15183 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19105 ,  H05K1/181 ,  H05K2201/10515 ,  H05K2201/1053 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor package assembly includes a first semiconductor package. The first semiconductor package includes a first body having a first device-attach surface and a first bump-attach surface opposite to the first device-attach surface. A second semiconductor package is bonded to the first device-attach surface of the first semiconductor package. The second package includes a second body having a second device-attach surface and a second bump-attach surface opposite to the second device-attach surface. A dynamic random access memory (DRAM) device is mounted on the second device-attach surface. A decoupling capacitor is mounted on the second device-attach surface. Conductive structures are disposed on the second bump-attach surface of the second package, connecting to the first bump-attach surface of the first body of the first semiconductor package.

Abstract translation: 半导体封装组件包括第一半导体封装。 第一半导体封装包括具有第一器件附着表面和与第一器件附着表面相对的第一凸起附着表面的第一本体。 第二半导体封装被结合到第一半导体封装的第一器件附着表面。 第二包装包括具有第二装置附着表面的第二主体和与第二装置附接表面相对的第二凸起附着表面。 动态随机存取存储器（DRAM）装置安装在第二装置附接表面上。 去耦电容器安装在第二器件附着表面上。 导电结构设置在第二封装的第二凸起附接表面上，连接到第一半导体封装的第一主体的第一凸起附着表面。