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    METHODS OF PROTECTING PERIPHERIES OF IN-PROCESS SEMICONDUCTOR WAFERS AND RELATED IN-PROCESS WAFERS AND SYSTEMS
    11.
    发明申请
    METHODS OF PROTECTING PERIPHERIES OF IN-PROCESS SEMICONDUCTOR WAFERS AND RELATED IN-PROCESS WAFERS AND SYSTEMS 有权
    保护过程中半导体波形外围的方法和相关的过程中的波形和系统

    公开(公告)号：US20160079094A1

    公开(公告)日：2016-03-17

    申请号：US14485973

    申请日：2014-09-15

    Applicant: Micron Technology, Inc.

    Inventor： Wei Zhou ,  Aibin Yu ,  Zhaohui Ma

    IPC: H01L21/56 ,  H01L23/31 ,  H01L21/324 ,  H01L21/311 ,  H01L21/306

    CPC classification number: H01L21/565 ,  H01L21/30604 ,  H01L21/31111 ,  H01L21/324 ,  H01L21/56 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3157 ,  H01L23/562 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Methods of processing semiconductor wafers may involve, for example, encapsulating an active surface and each side surface of a wafer of semiconductor material, a plurality of semiconductor devices located on the active surface of the wafer, an exposed side surface of an adhesive material located on a back side surface of the wafer, and at least a portion of a side surface of a carrier substrate secured to the wafer by the adhesive material in an encapsulation material. At least a portion of the side surface of the adhesive material may be exposed by removing at least a portion of the encapsulation material. The carrier substrate may be detached from the wafer. Processing systems and in-process semiconductor wafers are also disclosed.

    Abstract translation: 处理半导体晶片的方法可以包括例如封装半导体材料晶片的活性表面和每个侧表面，位于晶片的有效表面上的多个半导体器件，位于 晶片的背面表面和载体基板的侧表面的至少一部分通过胶粘材料固定在晶片上。 粘合剂材料的侧表面的至少一部分可以通过去除包封材料的至少一部分而暴露。 载体衬底可以从晶片分离。 还公开了处理系统和工艺中半导体晶片。

    Bond pad with micro-protrusions for direct metallic bonding
    13.
    发明授权
    Bond pad with micro-protrusions for direct metallic bonding 有权

    公开(公告)号：US10923448B2

    公开(公告)日：2021-02-16

    申请号：US15627314

    申请日：2017-06-19

    Applicant: Micron Technology, Inc.

    Inventor： Aibin Yu ,  Wei Zhou ,  Zhaohui Ma

    IPC: H01L23/00 ,  H01L23/48 ,  H01L21/768

    Abstract: A bond pad with micro-protrusions for direct metallic bonding. In one embodiment, a semiconductor device comprises a semiconductor substrate, a through-silicon via (TSV) extending through the semiconductor substrate, and a copper pad electrically connected to the TSV and having a coupling side. The semiconductor device further includes a copper element that projects away from the coupling side of the copper pad. In another embodiment, a bonded semiconductor assembly comprises a first semiconductor substrate with a first TSV and a first copper pad electrically coupled to the first TSV, wherein the first copper pad has a first coupling side. The bonded semiconductor assembly further comprises a second semiconductor substrate, opposite to the first semiconductor substrate, the second semiconductor substrate comprising a second copper pad having a second coupling side. A plurality of copper connecting elements extend between the first and second coupling sides of the first and second copper pads.

    METHODS OF PROCESSING WAFER-LEVEL ASSEMBLIES TO REDUCE WARPAGE, AND RELATED ASSEMBLIES
    15.
    发明申请
    METHODS OF PROCESSING WAFER-LEVEL ASSEMBLIES TO REDUCE WARPAGE, AND RELATED ASSEMBLIES 有权

    公开(公告)号：US20170179045A1

    公开(公告)日：2017-06-22

    申请号：US15446583

    申请日：2017-03-01

    Applicant: Micron Technology, Inc.

    Inventor： Aibin Yu ,  Wei Zhou ,  Zhaohui Ma ,  Bret K. Street

    IPC: H01L23/00 ,  H01L23/544 ,  H01L21/56

    CPC classification number: H01L23/562 ,  H01L21/561 ,  H01L23/544 ,  H01L25/0657 ,  H01L2223/5446 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Wafer-level methods of processing semiconductor devices may involve forming grooves partially through a molding material, the molding material located in streets and at least surrounding stacks of semiconductor dice located on a wafer. Wafer-level methods of preparing semiconductor devices may involve attaching a wafer to a carrier substrate and forming stacks of laterally spaced semiconductor dice on die locations of the wafer. Molding material may be disposed over the die stacks on a surface of the wafer to at least surround the stacks of semiconductor dice with the molding material. Grooves may be formed in the molding material by partially cutting through the molding material between at least some of the stacks of semiconductor dice along streets between the die stacks. The resulting wafer-level assembly may then, when exposed to elevated temperatures during, for example, debonding the wafer from a carrier, exhibit reduced propensity for warping.

    BOND PAD WITH MICRO-PROTRUSIONS FOR DIRECT METALLIC BONDING
    16.
    发明申请
    BOND PAD WITH MICRO-PROTRUSIONS FOR DIRECT METALLIC BONDING 审中-公开

    公开(公告)号：US20160093583A1

    公开(公告)日：2016-03-31

    申请号：US14496082

    申请日：2014-09-25

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Aibin Yu ,  Wei Zhou ,  Zhaohui Ma

    IPC: H01L23/00 ,  H01L23/48

    CPC classification number: H01L24/14 ,  H01L21/76898 ,  H01L23/00 ,  H01L23/481 ,  H01L24/00 ,  H01L24/09 ,  H01L24/81 ,  H01L2224/1701 ,  H01L2924/01029

    Abstract: A bond pad with micro-protrusions for direct metallic bonding. In one embodiment, a semiconductor device comprises a semiconductor substrate, a through-silicon via (TSV) extending through the semiconductor substrate, and a copper pad electrically connected to the TSV and having a coupling side. The semiconductor device further includes a copper element that projects away from the coupling side of the copper pad. In another embodiment, a bonded semiconductor assembly comprises a first semiconductor substrate with a first TSV and a first copper pad electrically coupled to the first TSV, wherein the first copper pad has a first coupling side. The bonded semiconductor assembly further comprises a second semiconductor substrate, opposite to the first semiconductor substrate, the second semiconductor substrate comprising a second copper pad having a second coupling side. A plurality of copper connecting elements extend between the first and second coupling sides of the first and second copper pads.

    Abstract translation: 具有用于直接金属结合的微突起的接合焊盘。 在一个实施例中，半导体器件包括半导体衬底，延伸穿过半导体衬底的贯通硅通孔（TSV）以及与TSV电连接并具有耦合侧的铜焊盘。 半导体器件还包括从铜焊盘的耦合侧突出的铜元件。 在另一个实施例中，键合的半导体组件包括具有第一TSV的第一半导体衬底和与第一TSV电耦合的第一铜焊盘，其中第一铜焊盘具有第一耦合侧。 键合半导体组件还包括与第一半导体衬底相对的第二半导体衬底，第二半导体衬底包括具有第二耦合侧的第二铜衬垫。 多个铜连接元件在第一和第二铜焊盘的第一和第二耦合侧之间延伸。

    Methods of processing wafer-level assemblies to reduce warpage, and related assemblies
    20.
    发明授权
    Methods of processing wafer-level assemblies to reduce warpage, and related assemblies 有权

    公开(公告)号：US09786612B2

    公开(公告)日：2017-10-10

    申请号：US15446583

    申请日：2017-03-01

    Applicant: Micron Technology, Inc.

    Inventor： Aibin Yu ,  Wei Zhou ,  Zhaohui Ma ,  Bret K. Street

    IPC: H01L21/78 ,  H01L23/00 ,  H01L21/56 ,  H01L23/544

    CPC classification number: H01L23/562 ,  H01L21/561 ,  H01L23/544 ,  H01L25/0657 ,  H01L2223/5446 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Wafer-level methods of processing semiconductor devices may involve forming grooves partially through a molding material, the molding material located in streets and at least surrounding stacks of semiconductor dice located on a wafer. Wafer-level methods of preparing semiconductor devices may involve attaching a wafer to a carrier substrate and forming stacks of laterally spaced semiconductor dice on die locations of the wafer. Molding material may be disposed over the die stacks on a surface of the wafer to at least surround the stacks of semiconductor dice with the molding material. Grooves may be formed in the molding material by partially cutting through the molding material between at least some of the stacks of semiconductor dice along streets between the die stacks. The resulting wafer-level assembly may then, when exposed to elevated temperatures during, for example, debonding the wafer from a carrier, exhibit reduced propensity for warping.

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