公开(公告)号：US20170179045A1

公开(公告)日：2017-06-22

申请号：US15446583

申请日：2017-03-01

Applicant: Micron Technology, Inc.

Inventor： Aibin Yu ,  Wei Zhou ,  Zhaohui Ma ,  Bret K. Street

IPC: H01L23/00 ,  H01L23/544 ,  H01L21/56

CPC classification number: H01L23/562 ,  H01L21/561 ,  H01L23/544 ,  H01L25/0657 ,  H01L2223/5446 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Wafer-level methods of processing semiconductor devices may involve forming grooves partially through a molding material, the molding material located in streets and at least surrounding stacks of semiconductor dice located on a wafer. Wafer-level methods of preparing semiconductor devices may involve attaching a wafer to a carrier substrate and forming stacks of laterally spaced semiconductor dice on die locations of the wafer. Molding material may be disposed over the die stacks on a surface of the wafer to at least surround the stacks of semiconductor dice with the molding material. Grooves may be formed in the molding material by partially cutting through the molding material between at least some of the stacks of semiconductor dice along streets between the die stacks. The resulting wafer-level assembly may then, when exposed to elevated temperatures during, for example, debonding the wafer from a carrier, exhibit reduced propensity for warping.

公开(公告)号：US12199068B2

公开(公告)日：2025-01-14

申请号：US17817690

申请日：2022-08-05

Applicant: Micron Technology, Inc.

Inventor： Owen R. Fay ,  Randon K. Richards ,  Aparna U. Limaye ,  Dong Soon Lim ,  Chan H. Yoo ,  Bret K. Street ,  Eiichi Nakano ,  Shijian Luo

IPC: H01L25/065 ,  H01L21/66 ,  H01L21/78 ,  H01L23/00 ,  H01L23/552 ,  H01L23/64 ,  H01L23/66 ,  H01L25/00 ,  H01L25/18 ,  H01Q1/22 ,  H01Q1/48

Abstract: Disclosed is a microelectronic device assembly comprising a substrate having conductors exposed on a surface thereof. Two or more microelectronic devices are stacked on the substrate, each microelectronic device comprising an active surface having bond pads operably coupled to conductive traces extending over a dielectric material to via locations beyond at least one side of the stack, and vias extending through the dielectric materials at the via locations and comprising conductive material in contact with at least some of the conductive traces of each of the two or more electronic devices and extending to exposed conductors of the substrate. Methods of fabrication and related electronic systems are also disclosed.

公开(公告)号：US20240332229A1

公开(公告)日：2024-10-03

申请号：US18619071

申请日：2024-03-27

Applicant: Micron Technology, Inc.

Inventor： Bharat Bhushan ,  Tzu Ching Hung ,  Kyle K. Kirby ,  Julia VanWinkle ,  Kyle B. Campbell ,  Bret K. Street

IPC: H01L23/00 ,  H01L21/66

CPC classification number: H01L24/06 ,  H01L22/32 ,  H01L24/03 ,  H01L24/08 ,  H01L2224/06517 ,  H01L2224/08146

Abstract: A semiconductor device is provided. The semiconductor device can have a front side at which circuitry is disposed. The circuitry can include a pad and a plurality of lines. A first layer of dielectric material can be disposed at the front side at least partially over the pad and the plurality of lines. A second layer of dielectric material can be disposed at the front side at least partially over the first layer of dielectric material. A dual damascene pad can extend through the first layer of dielectric material and the second layer of dielectric material to the pad. A dummy pad can be disposed in the second layer of dielectric material above the plurality of lines and spaced from the dual damascene pad. In doing so, a reliable semiconductor device can be implemented.

公开(公告)号：US20230395545A1

公开(公告)日：2023-12-07

申请号：US17830224

申请日：2022-06-01

Applicant: Micron Technology, Inc.

Inventor： Bharat Bhushan ,  Akshay N. Singh ,  Bret K. Street ,  Debjit Datta ,  Eiichi Nakano

IPC: H01L23/00 ,  H01L25/065

CPC classification number: H01L24/08 ,  H01L25/0652 ,  H01L24/80 ,  H01L24/95 ,  H01L2224/80047 ,  H01L2224/8001 ,  H01L2224/80896 ,  H01L2224/80895 ,  H01L2224/08148 ,  H01L2224/95093 ,  H01L2224/80204 ,  H01L2924/3512 ,  H01L2924/37001 ,  H01L2924/182 ,  H01L2924/1011

Abstract: Stacked semiconductor assemblies, and related systems and methods, are disclosed herein. A representative stacked semiconductor assembly can include a lowermost die and two or more modules carried by an upper surface of the lowermost die. Each of the module(s) can include a base die and one or more upper dies and/or an uppermost die carried by the base die. Each of the dies in the module is coupled via hybrid bonds between adjacent dies. Further, the base die in a lowermost module is coupled to the lowermost die by hybrid bonds. As a result of the modular construction, the lowermost die can have a first longitudinal footprint, the base die in each of the module(s) can have a second longitudinal footprint smaller than the first longitudinal footprint, and each of the upper die(s) and/or the uppermost die can have a third longitudinal footprint smaller than the second longitudinal footprint.

公开(公告)号：US11756844B2

公开(公告)日：2023-09-12

申请号：US17170120

申请日：2021-02-08

Applicant: Micron Technology, Inc.

Inventor： Wei Zhou ,  Bret K. Street ,  Mark E. Tuttle

IPC: H01L23/532 ,  H01L23/10 ,  H01L25/065 ,  H01L23/00 ,  H01L23/04 ,  H01L25/00

CPC classification number: H01L23/10 ,  H01L23/04 ,  H01L24/17 ,  H01L24/67 ,  H01L24/70 ,  H01L24/73 ,  H01L24/81 ,  H01L24/89 ,  H01L25/0657 ,  H01L25/50 ,  H01L24/16 ,  H01L2224/0401 ,  H01L2224/05647 ,  H01L2224/131 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/17517 ,  H01L2224/8109 ,  H01L2224/81075 ,  H01L2224/8182 ,  H01L2224/81122 ,  H01L2224/81815 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06575 ,  H01L2225/06593 ,  H01L2924/01029 ,  H01L2924/3025 ,  H01L2224/131 ,  H01L2924/014 ,  H01L2924/00014

Abstract: A semiconductor device includes a substrate; a die attached over the substrate; and a metal enclosure continuously encircling a space and extending vertically between the substrate and the die.

公开(公告)号：US20230197669A1

公开(公告)日：2023-06-22

申请号：US17881572

申请日：2022-08-04

Applicant: Micron Technology, Inc.

Inventor： Wei Zhou ,  Bret K. Street ,  Benjamin L. McClain ,  Mark E. Tuttle

IPC: H01L23/00 ,  H01L23/48

CPC classification number: H01L24/75 ,  H01L24/97 ,  H01L24/81 ,  H01L23/481 ,  H01L2224/81203 ,  H01L2224/95091 ,  H01L2224/75317

Abstract: A thermocompression bonding (TCB) apparatus can include a wall having a height measured in a first direction and configured to be positioned between a first pressing surface and a second pressing surface of a semiconductor bonding apparatus. The apparatus can include a cavity at least partially surrounded by the wall, the cavity sized to receive a semiconductor substrate and a stack of semiconductor dies positioned between the semiconductor substrate and the first pressing surface, the stack of semiconductor dies and semiconductor substrate having a combined unpressed stack height as measured in the first direction. In some embodiments, the unpressed stack height is greater than the height of the wall, and the wall is configured to be contacted by the first pressing surface to limit movement of the first pressing surface toward the second pressing surface during a semiconductor bonding process.

公开(公告)号：US11410962B2

公开(公告)日：2022-08-09

申请号：US17099625

申请日：2020-11-16

Applicant: Micron Technology, Inc.

Inventor： Wei Zhou ,  Bret K. Street ,  Benjamin L. McClain ,  Mark E. Tuttle

IPC: H01L21/00 ,  H01L23/00 ,  H01L23/48

Abstract: A thermocompression bonding (TCB) apparatus can include a wall having a height measured in a first direction and configured to be positioned between a first pressing surface and a second pressing surface of a semiconductor bonding apparatus. The apparatus can include a cavity at least partially surrounded by the wall, the cavity sized to receive a semiconductor substrate and a stack of semiconductor dies positioned between the semiconductor substrate and the first pressing surface, the stack of semiconductor dies and semiconductor substrate having a combined unpressed stack height as measured in the first direction. In some embodiments, the unpressed stack height is greater than the height of the wall, and the wall is configured to be contacted by the first pressing surface to limit movement of the first pressing surface toward the second pressing surface during a semiconductor bonding process.

公开(公告)号：US20220246569A1

公开(公告)日：2022-08-04

申请号：US17674487

申请日：2022-02-17

Applicant: Micron Technology, Inc.

Inventor： Kyle K. Kirby ,  Bret K. Street

IPC: H01L23/00 ,  H01L23/48 ,  H01L25/065 ,  H01L25/00

Abstract: Systems and methods for semiconductor devices having a substrate with bond pads, a die pair in a stacked configuration above the bond pads and having a first die having an oxide layer, a second die having an oxide layer attached to the first oxide layer, and conductive bonds electrically coupling the dies. Interconnects extend between the bond pads and the die pair, electrically coupling die pair to the substrate. The device may include a second die pair electrically coupled to: (1) the first die pair with secondary interconnects; and (2) the substrate with through-silicon vias extending through the first die pair. The top die of a die pair may be a thick die for use at the top of a pair stack. Pairs may be created by matching dies of a first silicon wafer to dies of a second silicon wafer, combination bonding the wafers, and dicing the die pairs.

公开(公告)号：US20210091037A1

公开(公告)日：2021-03-25

申请号：US17099655

申请日：2020-11-16

Applicant: Micron Technology, Inc.

Inventor： Wei Zhou ,  Bret K. Street ,  Benjamin L. McClain ,  Mark E. Tuttle

IPC: H01L23/00 ,  H01L23/48

Abstract: A thermocompression bonding (TCB) apparatus can include a wall having a height measured in a first direction and configured to be positioned between a first pressing surface and a second pressing surface of a semiconductor bonding apparatus. The apparatus can include a cavity at least partially surrounded by the wall, the cavity sized to receive a semiconductor substrate and a stack of semiconductor dies positioned between the semiconductor substrate and the first pressing surface, the stack of semiconductor dies and semiconductor substrate having a combined unpressed stack height as measured in the first direction. In some embodiments, the unpressed stack height is greater than the height of the wall, and the wall is configured to be contacted by the first pressing surface to limit movement of the first pressing surface toward the second pressing surface during a semiconductor bonding process.

公开(公告)号：US20210074671A1

公开(公告)日：2021-03-11

申请号：US17099625

申请日：2020-11-16

Applicant: Micron Technology, Inc.

Inventor： Wei Zhou ,  Bret K. Street ,  Benjamin L. McClain ,  Mark E. Tuttle

IPC: H01L23/00 ,  H01L23/48

Abstract: A thermocompression bonding (TCB) apparatus can include a wall having a height measured in a first direction and configured to be positioned between a first pressing surface and a second pressing surface of a semiconductor bonding apparatus. The apparatus can include a cavity at least partially surrounded by the wall, the cavity sized to receive a semiconductor substrate and a stack of semiconductor dies positioned between the semiconductor substrate and the first pressing surface, the stack of semiconductor dies and semiconductor substrate having a combined unpressed stack height as measured in the first direction. In some embodiments, the unpressed stack height is greater than the height of the wall, and the wall is configured to be contacted by the first pressing surface to limit movement of the first pressing surface toward the second pressing surface during a semiconductor bonding process.