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    Integrated circuitry, methods of forming memory cells, and methods of patterning platinum-containing material
    11.
    发明授权
    Integrated circuitry, methods of forming memory cells, and methods of patterning platinum-containing material 有权
    集成电路，形成记忆单元的方法，以及构图含铂材料的方法

    公开(公告)号：US08835891B2

    公开(公告)日：2014-09-16

    申请号：US14137477

    申请日：2013-12-20

    Applicant: Micron Technology, Inc.

    Inventor： Andrey V. Zagrebelny ,  Chet E. Carter

    IPC: H01L21/02 ,  H01L45/00 ,  H01L27/24 ,  H01L21/321 ,  H01L21/768 ,  H01L23/532

    CPC classification number: H01L45/1253 ,  H01L21/3212 ,  H01L21/7684 ,  H01L23/53242 ,  H01L27/2463 ,  H01L27/2472 ,  H01L45/08 ,  H01L45/085 ,  H01L45/147 ,  H01L45/16 ,  H01L45/1675 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Some embodiments include methods of patterning platinum-containing material. An opening may be formed to extend into an oxide. Platinum-containing material may be formed over and directly against an upper surface of the oxide, and within the opening. The platinum-containing material within the opening may be a plug having a lateral periphery. The lateral periphery of the plug may be directly against the oxide. The platinum-containing material may be subjected to polishing to remove the platinum-containing material from over the upper surface of the oxide. The polishing may delaminate the platinum-containing material from the oxide, and may remove the platinum-containing material from over the oxide with an effective selectivity for the platinum-containing material relative to the oxide of at least about 5:1. Some embodiments include methods of forming memory cells. Some embodiments include integrated circuitry having platinum-containing material within an opening in an oxide and directly against the oxide.

    Abstract translation: 一些实施方案包括图案化含铂材料的方法。 可以形成开口以延伸到氧化物中。 含铂的材料可以形成在氧化物的上表面上并且直接抵靠氧化物的上表面，并且在开口内形成。 开口内的含铂材料可以是具有侧面周边的塞子。 插塞的侧边缘可以直接抵靠氧化物。 可以对含铂材料进行抛光以从氧化物的上表面上除去含铂材料。 抛光可能使氧化物中的含铂材料分层，并且可以从氧化物上除去含铂材料，相对于含铂材料相对于氧化物的选择性至少约为5:1。 一些实施例包括形成存储器单元的方法。 一些实施例包括在氧化物的开口内并且直接抵靠氧化物的含铂材料的集成电路。

    METHODS OF FORMING MICROELECTRONIC DEVICES
    15.
    发明公开
    METHODS OF FORMING MICROELECTRONIC DEVICES 审中-公开

    公开(公告)号：US20230389318A1

    公开(公告)日：2023-11-30

    申请号：US18359792

    申请日：2023-07-26

    Applicant: Micron Technology, Inc.

    Inventor： Collin Howder ,  Justin D. Shepherdson ,  Chet E. Carter

    IPC: H10B43/27 ,  H10B43/50

    CPC classification number: H10B43/27 ,  H10B43/50

    Abstract: A microelectronic device may include a source structure and a stack structure. The stack structure may include a vertically alternating sequence of insulative structures and conductive structures. Filled slits may extend through the stack structure and into the source structure, the slits dividing the stack structure into multiple blocks. Memory cell pillars may extend through the stack structure and into the source structure, the memory cell pillars and the filled slits terminated at substantially the same depth within the source structure as one another.

    Memory Arrays and Methods Used in Forming a Memory Array Comprising Strings of Memory Cells
    16.
    发明公开
    Memory Arrays and Methods Used in Forming a Memory Array Comprising Strings of Memory Cells 审中-公开

    公开(公告)号：US20230337429A1

    公开(公告)日：2023-10-19

    申请号：US18212899

    申请日：2023-06-22

    Applicant: Micron Technology, Inc.

    Inventor： Collin Howder ,  Chet E. Carter

    IPC: H10B43/27 ,  H01L21/822 ,  H10B41/27 ,  H10B41/35 ,  H10B43/35

    CPC classification number: H10B43/27 ,  H01L21/8221 ,  H10B41/27 ,  H10B41/35 ,  H10B43/35

    Abstract: A method used in forming a memory array comprises forming a substrate comprising a conductor tier comprising an upper conductor material and a lower conductor material, and a stack comprising vertically-alternating first tiers and second tiers above the conductor tier. Horizontally-elongated trenches are formed through the stack to the upper conductor material and the lower conductor material. At least one of the upper and lower conductor materials have an exposed catalytic surface in the trenches. Metal material is electrolessly deposited onto the catalytic surface to cover the upper conductor material and the lower conductor material within the trenches. Channel-material strings of memory cells are formed and extend through the second tiers and the first tiers. Other embodiments, including structure independent of method, are disclosed.

    Memory arrays and methods used in forming a memory array
    19.
    发明授权
    Memory arrays and methods used in forming a memory array 有权

    公开(公告)号：US11411015B2

    公开(公告)日：2022-08-09

    申请号：US17151344

    申请日：2021-01-18

    Applicant: Micron Technology, Inc.

    Inventor： Collin Howder ,  Chet E. Carter

    IPC: H01L27/11556 ,  H01L27/11582 ,  H01L27/11519 ,  H01L27/11565 ,  H01L21/311 ,  H01L21/3213

    Abstract: A method used in forming a memory array comprises forming a substrate comprising a conductor tier comprising upper conductor material, lower metal material, and intervening metal material vertically between the upper conductor material and the lower metal material. The intervening metal material, the upper conductor material, and the lower metal material are of different compositions relative one another. The intervening metal material has a reduction potential that is less than 0.7V away from the reduction potential of the upper conductor material. A stack comprising vertically-alternating insulative tiers and conductive tiers is formed above the conductor tier. Channel material is formed through the insulative tiers and the conductive tiers. Horizontally-elongated trenches are formed through the stack to the conductor tier. Elevationally-extending strings of memory cells are formed in the stack. Individual of the memory cells comprise the channel material, a gate region that is part of a conductive line in individual of the conductive tiers, and a memory structure laterally between the gate region and the channel material in the individual conductive tiers. Other methods and structure independent of method are disclosed.

    Memory Arrays and Methods Used in Forming a Memory Array Comprising Strings of Memory Cells
    20.
    发明申请
    Memory Arrays and Methods Used in Forming a Memory Array Comprising Strings of Memory Cells 有权

    公开(公告)号：US20220231046A1

    公开(公告)日：2022-07-21

    申请号：US17714924

    申请日：2022-04-06

    Applicant: Micron Technology, Inc.

    Inventor： Collin Howder ,  Chet E. Carter

    IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11556 ,  H01L27/11524 ,  H01L21/822

    Abstract: A method used in forming a memory array comprises forming a substrate comprising a conductor tier comprising an upper conductor material and a lower conductor material, and a stack comprising vertically-alternating first tiers and second tiers above the conductor tier. Horizontally-elongated trenches are formed through the stack to the upper conductor material and the lower conductor material. At least one of the upper and lower conductor materials have an exposed catalytic surface in the trenches. Metal material is electrolessly deposited onto the catalytic surface to cover the upper conductor material and the lower conductor material within the trenches. Channel-material strings of memory cells are formed and extend through the second tiers and the first tiers. Other embodiments, including structure independent of method, are disclosed.

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