公开(公告)号：US09070393B2

公开(公告)日：2015-06-30

申请号：US14196363

申请日：2014-03-04

Applicant: PANASONIC CORPORATION

Inventor： Shingo Yoshioka ,  Hiroaki Fujiwara ,  Hiromitsu Takashita ,  Tsuyoshi Takeda

IPC: H01L23/04 ,  G11B5/48 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H05K1/11 ,  H05K1/18 ,  H05K3/18 ,  H01L23/498 ,  H01L21/48 ,  H01L21/66 ,  H01L23/31 ,  H01L21/56 ,  H01L23/14

CPC classification number: G11B5/486 ,  H01L21/4846 ,  H01L21/565 ,  H01L22/12 ,  H01L23/145 ,  H01L23/3121 ,  H01L23/49866 ,  H01L24/24 ,  H01L24/25 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/82 ,  H01L24/83 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05554 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/24011 ,  H01L2224/2405 ,  H01L2224/24051 ,  H01L2224/24137 ,  H01L2224/24146 ,  H01L2224/24226 ,  H01L2224/245 ,  H01L2224/25175 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/73267 ,  H01L2224/82009 ,  H01L2224/82039 ,  H01L2224/82101 ,  H01L2224/82385 ,  H01L2224/82399 ,  H01L2224/82931 ,  H01L2224/82947 ,  H01L2224/8385 ,  H01L2224/85 ,  H01L2224/92244 ,  H01L2225/06524 ,  H01L2225/06551 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/00015 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01051 ,  H01L2924/01056 ,  H01L2924/01057 ,  H01L2924/01058 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15798 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/386 ,  H01L2924/3862 ,  H05K1/111 ,  H05K1/181 ,  H05K3/184 ,  H05K2201/0376 ,  H05K2201/09472 ,  H05K2203/1461 ,  Y02P70/611 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/0401 ,  H01L2224/45015 ,  H01L2924/207

Abstract: One aspect of the present invention is a three-dimensional structure in which a wiring is formed on a surface, the three-dimensional structure having an insulating resin layer that contains a filler formed from at least one element selected from typical non-metal elements and typical metal elements, wherein a recessed gutter for wiring is formed on a surface of the insulating resin layer, and at least a part of a wiring conductor is embedded in the recessed gutter for wiring.

Abstract translation: 本发明的一个方面是一种三维结构，其中在表面上形成布线，所述三维结构具有绝缘树脂层，所述绝缘树脂层含有由选自典型非金属元素中的至少一种元素形成的填料和 典型的金属元件，其中在绝缘树脂层的表面上形成用于布线的凹槽，并且布线导体的至少一部分嵌入到凹槽中用于布线。

公开(公告)号：US20140191406A1

公开(公告)日：2014-07-10

申请号：US14235766

申请日：2012-10-18

Applicant: PANASONIC CORPORATION

Inventor： Hiromitsu Takashita ,  Tsuyoshi Takeda ,  Keiko Kashihara ,  Hiroaki Fujiwara ,  Shingo Yoshioka

IPC: H01L21/768 ,  H01L23/48 ,  H01L21/56

CPC classification number: H01L21/76877 ,  H01L21/56 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/02311 ,  H01L2224/0236 ,  H01L2224/02379 ,  H01L2224/033 ,  H01L2224/03464 ,  H01L2224/0347 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/1411 ,  H01L2224/19 ,  H01L2224/2101 ,  H01L2224/2105 ,  H01L2224/96 ,  H01L2924/0001 ,  H01L2924/12042 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/18162 ,  H01L2924/3511 ,  H01L2924/014 ,  H01L2224/13099 ,  H01L2924/00012 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/00

Abstract: One aspect of the present invention resides in a manufacturing method for a semiconductor package, including a covering step of forming a covering insulating layer that covers the surface of a semiconductor element, a film-forming step of forming a resin film on the surface of the covering insulating layer, a circuit pattern-forming step of forming a circuit pattern portion including recesses reaching the surfaces of electrodes of the semiconductor element and a circuit groove having a desired shape and a desired depth, a catalyst-depositing step of depositing a plating catalyst or a precursor thereof on the surface of the circuit pattern portion, a film-separating step of separating the resin film from the covering insulating layer, and a plating processing step of forming a circuit electrically connected to the electrodes, by applying electroless plating to the covering insulating layer, from which the resin film is separated.

Abstract translation: 本发明的一个方面在于一种半导体封装的制造方法，包括形成覆盖半导体元件表面的覆盖绝缘层的覆盖步骤，在该表面上形成树脂膜的成膜步骤 覆盖绝缘层的电路图案形成步骤，形成包括到达半导体元件的电极表面的凹部的电路图案部分和具有期望形状和期望深度的电路槽的电路图案形成步骤，沉积镀催化剂的催化剂沉积步骤 或其前体在电路图案部分的表面上，将分离树脂膜与覆盖绝缘层分离的膜分离步骤，以及电镀处理步骤，形成电连接到电极的电路，通过将化学镀施加到 覆盖绝缘层，树脂膜从中分离。

公开(公告)号：US08759148B2

公开(公告)日：2014-06-24

申请号：US13836706

申请日：2013-03-15

Applicant: Panasonic Corporation

Inventor： Shingo Yoshioka ,  Hiroaki Fujiwara

IPC: H01L21/00

CPC classification number: H05K1/11 ,  G11B5/486 ,  H01L21/565 ,  H01L22/12 ,  H01L23/3121 ,  H01L24/03 ,  H01L24/05 ,  H01L24/24 ,  H01L24/25 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/82 ,  H01L24/83 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/24011 ,  H01L2224/2405 ,  H01L2224/24051 ,  H01L2224/24137 ,  H01L2224/24146 ,  H01L2224/24226 ,  H01L2224/245 ,  H01L2224/25175 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/73267 ,  H01L2224/82009 ,  H01L2224/82039 ,  H01L2224/82101 ,  H01L2224/82931 ,  H01L2224/82947 ,  H01L2224/8385 ,  H01L2224/85 ,  H01L2224/92244 ,  H01L2225/06524 ,  H01L2225/06551 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/00015 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01051 ,  H01L2924/01056 ,  H01L2924/01057 ,  H01L2924/01058 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H05K1/111 ,  H05K1/117 ,  H05K1/181 ,  H05K3/184 ,  H05K2201/0376 ,  H05K2201/09472 ,  Y02P70/611 ,  Y10T428/1171 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A method of mounting a semiconductor chip includes: forming a resin coating on a surface of a path connecting a bonding pad on a surface of a semiconductor chip and an electrode pad formed on a surface of an insulating base material; forming, by laser beam machining, a wiring gutter having a depth that is equal to or greater than a thickness of the resin coating along the path for connecting the bonding pad and the electrode pad; depositing a plating catalyst on a surface of the wiring gutter; removing the resin coating; and forming an electroless plating coating only at a site where the plating catalyst remains.

Abstract translation: 安装半导体芯片的方法包括：在连接半导体芯片的表面上的接合焊盘和形成在绝缘基材的表面上的电极焊盘的路径的表面上形成树脂涂层; 通过激光束加工形成具有等于或大于沿着用于连接焊盘和电极焊盘的路径的树脂涂层的厚度的深度的布线槽; 在布线槽的表面上沉积电镀催化剂; 去除树脂涂层; 并且仅在电镀催化剂保留的部位形成化学镀层。