公开(公告)号：US11764489B2

公开(公告)日：2023-09-19

申请号：US17568596

申请日：2022-01-04

Applicant: QUALCOMM Incorporated

Inventor： Milind Shah ,  Chin-Kwan Kim ,  Jaehyun Yeon ,  Rajneesh Kumar ,  Suhyung Hwang

IPC: H01Q23/00 ,  H01Q1/24 ,  H01Q21/06 ,  H01Q21/30 ,  H01Q9/04

CPC classification number: H01Q23/00 ,  H01Q1/241 ,  H01Q1/243 ,  H01Q9/0414 ,  H01Q21/065 ,  H01Q21/068 ,  H01Q21/30

Abstract: An antenna-in-package (AiP) module is described. The AiP module includes an antenna sub-module. The antenna sub-module is composed of a first package substrate including an antenna side surface having a first group of antennas placed along a first portion of the antenna side surface and a second group of antennas placed along a second portion of the antenna side surface. The first package substrate is composed of a non-linear portion between the first group of antennas and the second group of antennas. The AiP module includes an active circuit sub-module placed on an active side surface of the first package substrate opposite the first group of antennas or the second group of antennas on the antenna side surface of the first package substrate. The active circuit includes a power management (PM) chip and a radio frequency (RF) chip coupled to a second package substrate coupled to the first package substrate.

公开(公告)号：US11756894B2

公开(公告)日：2023-09-12

申请号：US16879517

申请日：2020-05-20

Applicant: QUALCOMM Incorporated

Inventor： Jeahyeong Han ,  Rajneesh Kumar ,  Jeongil Jay Kim ,  Chin-Kwan Kim

IPC: H01L23/552 ,  H01L21/48 ,  H01L23/498 ,  H01L23/66 ,  H01L23/00 ,  H01Q1/22 ,  H01Q1/52

CPC classification number: H01L23/552 ,  H01L21/4853 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/66 ,  H01L24/16 ,  H01Q1/2283 ,  H01Q1/526 ,  H01L2223/6677 ,  H01L2224/16227 ,  H01L2924/3025

Abstract: Radio-frequency (RF) integrated circuit (IC) (RFIC) packages employing a substrate sidewall partial shield for electro-magnetic interference (EMI) shielding. A RFIC package includes an IC die layer that includes a RFIC die(s) mounted on a substrate that includes substrate metallization layers, a substrate core, and substrate antenna layers. The RFIC package includes an EMI shield surrounding the IC die layer and extending down shared sidewalls of the IC die layer and the substrate. The EMI shield extends down the sidewalls of the IC die layer and substrate metallization layers of the substrate to at least the interface between the substrate metallization layers and the substrate core, and without extending adjacent to the sidewall of the substrate antenna layers. In this manner, antenna performance of the antenna module may not be degraded, because extending the EMI shield down sidewalls of the substrate antenna layers can create a resonance cavity in the substrate.

公开(公告)号：US11239573B2

公开(公告)日：2022-02-01

申请号：US16886086

申请日：2020-05-28

Applicant: QUALCOMM Incorporated

Inventor： Milind Shah ,  Chin-Kwan Kim ,  Jaehyun Yeon ,  Rajneesh Kumar ,  Suhyung Hwang

IPC: H01Q23/00 ,  H01Q21/06 ,  H01Q21/30 ,  H01Q1/24 ,  H01Q9/04

Abstract: An antenna-in-package (AiP) module is described. The AiP module includes an antenna sub-module. The antenna sub-module is composed of a first package substrate including an antenna side surface having a first group of antennas placed along a first portion of the antenna side surface and a second group of antennas placed along a second portion of the antenna side surface. The first package substrate is composed of a non-linear portion between the first group of antennas and the second group of antennas. The AiP module includes an active circuit sub-module placed on an active side surface of the first package substrate opposite the first group of antennas or the second group of antennas on the antenna side surface of the first package substrate.

公开(公告)号：US20170098633A1

公开(公告)日：2017-04-06

申请号：US15069525

申请日：2016-03-14

Applicant: QUALCOMM Incorporated

Inventor： Rajneesh Kumar ,  Chin-Kwan Kim ,  Brian Roggeman

IPC: H01L25/10 ,  H01L23/538 ,  H01L23/31

CPC classification number: H01L25/105 ,  H01L21/568 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/5386 ,  H01L24/13 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/32 ,  H01L24/92 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13111 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/1076 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/3511 ,  H01L2924/01029

Abstract: A package on package (PoP) device that includes a first package, a second package that is coupled to the first package, and at least one gap controller located between the first package and the second package, where the at least one gap controller is configured to provide a minimum gap between the first package and the second package. The first package includes a first electronic package component (e.g., first die). In some implementations, the at least one gap controller is coupled to the first package, but free of coupling with the second package. The at least one gap controller is located on or about a center of the first package. The at least one gap controller may be located between the first electronic package component (e.g., first die) and the second package. The package on package (PoP) device may include an encapsulation layer between the first package and the second package.

公开(公告)号：US20160172299A1

公开(公告)日：2016-06-16

申请号：US14610876

申请日：2015-01-30

Applicant: QUALCOMM Incorporated

Inventor： Vladimir Noveski ,  Milind Pravin Shah ,  Rajneesh Kumar

IPC: H01L23/528 ,  H01L23/31 ,  H01L23/00 ,  H01L23/522 ,  H01L23/498

CPC classification number: H01L23/5283 ,  H01L23/3157 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5226 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/27 ,  H01L24/29 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0346 ,  H01L2224/0347 ,  H01L2224/0348 ,  H01L2224/03602 ,  H01L2224/03914 ,  H01L2224/05546 ,  H01L2224/05568 ,  H01L2224/05571 ,  H01L2224/05647 ,  H01L2224/1111 ,  H01L2224/11334 ,  H01L2224/11438 ,  H01L2224/13007 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16014 ,  H01L2224/16111 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/2711 ,  H01L2224/27438 ,  H01L2224/29006 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/81101 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81801 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2924/2064 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: An integrated device package that includes a die, a substrate, a fill and a conductive interconnect. The die includes a pillar, where the pillar has a first pillar width. The substrate (e.g., package substrate, interposer) includes a dielectric layer and a substrate interconnect (e.g., surface interconnect, embedded interconnect). The fill is located between the die and the substrate. The conductive interconnect is located within the fill. The conductive interconnect includes a first interconnect width that is about the same or less than the first pillar width. The conductive interconnect is coupled to the pillar and the substrate interconnect. The fill is a non-conductive photosensitive material. The fill is a photosensitive film. The substrate interconnect includes a second interconnect width that is equal or greater than the first pillar width. The conductive interconnect includes one of at least a paste, a solder and/or an enhanced solder comprising a polymeric material.

Abstract translation: 一种集成器件封装，其包括管芯，衬底，填充物和导电互连。 模具包括支柱，其中柱具有第一柱宽度。 衬底（例如，封装衬底，插入器）包括电介质层和衬底互连（例如，表面互连，嵌入式互连）。 填充物位于管芯和衬底之间。 导电互连位于填充物内。 导电互连包括大约等于或小于第一柱宽度的第一互连宽度。 导电互连耦合到柱和衬底互连。 填充物是非导电感光材料。 填充物是感光膜。 衬底互连包括等于或大于第一柱宽度的第二互连宽度。 导电互连包括至少一种包含聚合材料的糊状物，焊料和/或增强焊料中的至少一种。

公开(公告)号：US20150061143A1

公开(公告)日：2015-03-05

申请号：US14318490

申请日：2014-06-27

Applicant: QUALCOMM Incorporated

Inventor： Chin-Kwan Kim ,  Rajneesh Kumar ,  Omar James Bchir

IPC: H01L23/528 ,  H01L23/00 ,  H01L21/768

CPC classification number: H01L23/528 ,  H01L21/768 ,  H01L23/498 ,  H01L23/49827 ,  H01L24/06 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/131 ,  H01L2224/14133 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/17051 ,  H01L2224/81191 ,  H01L2224/81385 ,  H01L2224/81801 ,  H01L2924/3841 ,  H05K1/0296 ,  H05K1/111 ,  H05K3/4682 ,  H05K2201/0376 ,  H05K2201/094 ,  Y02P70/611 ,  H01L2924/00014 ,  H01L2924/014

Abstract: Some novel features pertain to a substrate that includes a first dielectric layer, a first interconnect, a first cavity, and a second interconnect. The first dielectric layer includes first and second surfaces. The first interconnect is embedded in the first dielectric layer. The first interconnect includes a first side and a second side. The first side is surrounded by the first dielectric layer, where at least a part of the second side is free of contact with the first dielectric layer. The first cavity traverses the first surface of the first dielectric layer to the second side of the first interconnect, where the first cavity overlaps the first interconnect. The second interconnect includes a third side and a fourth side, where the third side is coupled to the first surface of the first dielectric layer.

Abstract translation: 一些新颖的特征涉及包括第一介电层，第一互连，第一腔和第二互连的衬底。 第一介电层包括第一和第二表面。 第一互连嵌入在第一电介质层中。 第一互连包括第一侧和第二侧。 第一侧被第一介电层包围，其中第二侧的至少一部分与第一介电层不接触。 第一空腔穿过第一介电层的第一表面到第一互连的第二侧，其中第一腔与第一互连重叠。 第二互连包括第三侧和第四侧，其中第三侧耦合到第一介电层的第一表面。

公开(公告)号：US11245175B2

公开(公告)日：2022-02-08

申请号：US16145100

申请日：2018-09-27

Applicant: QUALCOMM Incorporated

Inventor： Seong Heon Jeong ,  Rajneesh Kumar ,  Mohammad Ali Tassoudji ,  Darryl Jessie ,  Gurkanwal Sahota ,  Kevin Hsi Huai Wang ,  Jeong Il Kim ,  Taesik Yang ,  Thomas Myers ,  Neil Burns ,  Julio Zegarra ,  Clinton James Wilber ,  Jordan Szabo

IPC: H01Q1/24 ,  H01Q1/22 ,  H01L25/065 ,  H01L23/28 ,  H01L23/552 ,  H01L23/64 ,  H01L23/66 ,  H01Q1/52 ,  H01Q9/06 ,  H01Q9/26 ,  H01Q21/28 ,  H01L23/31 ,  H01Q9/04

Abstract: An antenna module is described. The antenna module include a ground plane in a multilayer substrate. The antenna module also includes a mold on the multilayer substrate. The antenna module further includes a conductive wall separating a first portion of the mold from a second portion of the mold. The conductive wall is electrically coupled to the ground plane. A conformal shield may be placed on a surface of the second portion of the mold. The conformal shield is electrically coupled to the ground plane.

公开(公告)号：US20210410274A1

公开(公告)日：2021-12-30

申请号：US17100121

申请日：2020-11-20

Applicant: QUALCOMM Incorporated

Inventor： Jeahyeong Han ,  Suhyung Hwang ,  Mina Iskander ,  Rajneesh Kumar ,  Darryl Sheldon Jessie

IPC: H05K1/02 ,  H01Q21/06 ,  H01Q1/48 ,  H01Q1/22

Abstract: Systems for shielding bent signal lines provide ways to couple different antenna arrays for radio frequency (RF) integrated circuits (ICs) (RFICs) associated therewith where the antenna arrays are oriented in different directions. Because the antenna arrays are oriented in different directions, the antenna structures containing the antennas may be arranged in different planes, and signal lines extending therebetween may include a bend. To prevent electromagnetic interference (EMI) or electromagnetic crosstalk (EMC) from negatively impacting signals on the signal lines, the signal lines may be shielded. The shields may further include vias connecting the mesh ground planes and positioned exteriorly of the signal lines. The density of the vias may be varied to provide a desired rigidity in planes containing the antenna arrays while providing a desired flexibility at a desired bending location in the signal lines to help bending process accuracy.

公开(公告)号：US10163871B2

公开(公告)日：2018-12-25

申请号：US15097719

申请日：2016-04-13

Applicant: QUALCOMM Incorporated

Inventor： Rajneesh Kumar ,  Chin-Kwan Kim ,  Milind Shah

IPC: H01L25/10 ,  H01L23/552 ,  H01L23/66 ,  H01L25/065 ,  H04W4/80 ,  H01L25/00 ,  H04W4/00 ,  H01L23/00 ,  H01L25/16 ,  H01L21/56

Abstract: An integrated device that includes a printed circuit board (PCB) and a package on package (PoP) device coupled to the printed circuit board (PCB). The package on package (PoP) device includes a first package that includes a first electronic package component (e.g., first die) and a second package coupled to the first package. The integrated device includes a first encapsulation layer formed between the first package and the second package. The integrated device includes a second encapsulation layer that at least partially encapsulates the package on package (PoP) device. The integrated device is configured to provide cellular functionality, wireless fidelity functionality and Bluetooth functionality. In some implementations, the first encapsulation layer is separate from the second encapsulation layer. In some implementations, the second encapsulation layer includes the first encapsulation layer. The package on package (PoP) device includes a gap controller located between the first package and the second package.

公开(公告)号：US09947642B2

公开(公告)日：2018-04-17

申请号：US15069525

申请日：2016-03-14

Applicant: QUALCOMM Incorporated

Inventor： Rajneesh Kumar ,  Chin-Kwan Kim ,  Brian Roggeman

IPC: H01L25/10 ,  H01L23/31 ,  H01L23/538

CPC classification number: H01L25/105 ,  H01L21/568 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/5386 ,  H01L24/13 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/32 ,  H01L24/92 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13111 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/1076 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/3511 ,  H01L2924/01029

Abstract: A package on package (PoP) device that includes a first package, a second package that is coupled to the first package, and at least one gap controller located between the first package and the second package, where the at least one gap controller is configured to provide a minimum gap between the first package and the second package. The first package includes a first electronic package component (e.g., first die). In some implementations, the at least one gap controller is coupled to the first package, but free of coupling with the second package. The at least one gap controller is located on or about a center of the first package. The at least one gap controller may be located between the first electronic package component (e.g., first die) and the second package. The package on package (PoP) device may include an encapsulation layer between the first package and the second package.