公开(公告)号：US20140284705A1

公开(公告)日：2014-09-25

申请号：US14300327

申请日：2014-06-10

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Satoshi EGUCHI ,  Yuya ABIKO ,  Junichi KOGURE

IPC: H01L29/78

CPC classification number: H01L29/7802 ,  H01L21/02639 ,  H01L21/26506 ,  H01L21/26566 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/161 ,  H01L29/165 ,  H01L29/41766 ,  H01L29/66712 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7813 ,  H01L29/7842 ,  H01L29/7848

Abstract: In the manufacturing steps of a super-junction power MOSFET having a drift region having a super junction structure, after the super junction structure is formed, introduction of a body region and the like and heat treatment related thereto are typically performed. However, in the process thereof, a dopant in each of P-type column regions and the like included in the super junction structure is diffused to result in a scattered dopant profile. This causes problems such as degradation of a breakdown voltage when a reverse bias voltage is applied between a drain and a source and an increase in ON resistance. According to the present invention, in a method of manufacturing a silicon-based vertical planar power MOSFET, a body region forming a channel region is formed by selective epitaxial growth.

Abstract translation: 在具有超结结构的漂移区域的超结功率MOSFET的制造步骤中，在形成超结结构之后，通常进行体区等的引入和与其相关的热处理。 然而，在其过程中，包含在超结结构中的每个P型列区域等中的掺杂剂被扩散以产生散射掺杂剂分布。 这导致了当在漏极和源极之间施加反向偏置电压和导通电阻增加时诸如击穿电压劣化的问题。 根据本发明，在制造硅基垂直平面功率MOSFET的方法中，通过选择性外延生长形成形成沟道区的体区。

公开(公告)号：US20140206162A1

公开(公告)日：2014-07-24

申请号：US14154260

申请日：2014-01-14

Applicant: Renesas Electronics Corporation

Inventor： Satoshi EGUCHI ,  Daisuke TANIGUCHI

IPC: H01L29/66

CPC classification number: H01L21/30625 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/3081 ,  H01L21/3083 ,  H01L21/3086 ,  H01L21/78 ,  H01L23/544 ,  H01L24/03 ,  H01L24/05 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/6634 ,  H01L29/66674 ,  H01L29/66681 ,  H01L29/66712 ,  H01L29/66727 ,  H01L29/7395 ,  H01L29/7396 ,  H01L29/7802 ,  H01L29/7816 ,  H01L29/8611 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/5446 ,  H01L2224/02166 ,  H01L2224/0345 ,  H01L2224/05624 ,  H01L2924/00014 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2224/05599 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A manufacturing method of a power MOSFET employs a hard mask film over a portion of the wafer surface as a polishing stopper, between two successive polishing steps. After embedded epitaxial growth is performed in a state where a hard mask film for forming trenches is present in at least a scribe region of a wafer, primary polishing is performed by using the hard mask film as a stopper, and secondary polishing is then performed after the hard mask film is removed.

Abstract translation: 功率MOSFET的制造方法在两个连续的抛光步骤之间使用在晶片表面的一部分上的硬掩模膜作为抛光停止器。 在晶片的至少划片区域中存在用于形成沟槽的硬掩模膜的状态下进行嵌入式外延生长之后，通过使用硬掩模膜作为阻挡层进行一次抛光，然后在 去除硬掩模膜。

公开(公告)号：US20140191309A1

公开(公告)日：2014-07-10

申请号：US14109208

申请日：2013-12-17

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Satoshi EGUCHI ,  Yoshito NAKAZAWA ,  Tomohiro TAMAKI

IPC: H01L29/06 ,  H01L29/78

CPC classification number: H01L29/0619 ,  H01L29/0626 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/0886 ,  H01L29/402 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/66727 ,  H01L29/7802 ,  H01L29/7811

Abstract: When forming a super junction by the embedded epitaxial method, adjusting a taper angle of dry etching to form an inclined column is generally performed in trench forming etching, in order to prevent a reduction in breakdown voltage due to fluctuations in concentration in an embedded epitaxial layer. However, according to the examination by the present inventors, it has been made clear that such a method makes design more and more difficult in response to the higher breakdown voltage. In the present invention, the concentration in an intermediate substrate epitaxy column area in each substrate epitaxy column area configuring a super junction is made more than that in other areas within the substrate epitaxy column area, in a vertical power MOSFET having the super junction by the embedded epitaxial method.

Abstract translation: 当通过嵌入式外延法形成超级结时，通常在沟槽形成蚀刻中进行干蚀刻的锥角调整以形成倾斜的列，以便防止由嵌入的外延层中的浓度波动引起的击穿电压的降低 。 然而，根据本发明人的考察，已经清楚的是，这种方法使得设计越来越难以响应较高的击穿电压。 在本发明中，在构成超结的每个衬底外延柱区域中的中间衬底外延柱区域中的浓度比在衬底外延柱区域内的其它区域的浓度高， 嵌入式外延法。

公开(公告)号：US20240204098A1

公开(公告)日：2024-06-20

申请号：US18592332

申请日：2024-02-29

Applicant: Renesas Electronics Corporation

Inventor： Atsushi SAKAI ,  Katsumi EIKYU ,  Satoshi EGUCHI ,  Nobuo MACHIDA ,  Koichi ARAI ,  Yasuhiro OKAMOTO ,  Kenichi HISADA ,  Yasunori YAMASHITA

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/16 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/7813 ,  H01L29/0865 ,  H01L29/1608 ,  H01L29/4236 ,  H01L29/66068 ,  H01L29/66734

Abstract: To improve characteristics of a semiconductor device. A first p-type semiconductor region having an impurity of a conductivity type opposite from that of a drift layer is arranged in the drift layer below a trench, and a second p-type semiconductor region is further arranged that is spaced at a distance from a region where the trench is formed as seen from above and that has the impurity of the conductivity type opposite from that of the drift layer. The second p-type semiconductor region is configured by a plurality of regions arranged at a space in a Y direction (depth direction in the drawings). Thus, it is possible to reduce the specific on-resistance while maintaining the breakdown voltage of the gate insulating film by providing the first and second p-type semiconductor regions and further by arranging the second p-type semiconductor region spaced by the space.

公开(公告)号：US20190207001A1

公开(公告)日：2019-07-04

申请号：US16299025

申请日：2019-03-11

Applicant: Renesas Electronics Corporation

Inventor： Yuya ABIKO ,  Natsuo YAMAGUCHI ,  Satoshi EGUCHI

IPC: H01L29/10 ,  H01L21/265 ,  H01L29/06 ,  H01L29/16 ,  H01L29/78 ,  H01L21/308 ,  H01L29/40 ,  H01L21/02 ,  H01L29/66 ,  H01L29/739

CPC classification number: H01L29/1095 ,  H01L21/02529 ,  H01L21/26586 ,  H01L21/308 ,  H01L29/0634 ,  H01L29/1608 ,  H01L29/404 ,  H01L29/66053 ,  H01L29/66068 ,  H01L29/66712 ,  H01L29/66734 ,  H01L29/7395 ,  H01L29/7802 ,  H01L29/7813

Abstract: In a vertical power MOSFET having a superjunction structure, the withstand voltage of the power MOSFET can be ensured even if the aspect ratios of an n-type column region and a p-type column region are increased so as to vary the impurity concentration of the p-type column region. P-type semiconductor regions PR1 are formed on the sides of an n-type column NC1 adjacent to a p-type column region PC1. In this configuration, the p-type semiconductor region PR1 is formed from the upper end of the n-type column region NC1 to about a half depth of a height from the upper end to the lower end of the side of the n-type column region NC1. This inclines the sides of the overall p-type column region including the p-type semiconductor regions PR1 and the p-type column region PC1.

公开(公告)号：US20180076313A1

公开(公告)日：2018-03-15

申请号：US15640375

申请日：2017-06-30

Applicant: Renesas Electronics Corporation

Inventor： Yuya ABIKO ,  Satoshi EGUCHI ,  Shigeaki SAITO ,  Daisuke TANIGUCHI ,  Natsuo YAMAGUCHI

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/08

CPC classification number: H01L29/7802 ,  H01L21/2205 ,  H01L21/2251 ,  H01L21/2253 ,  H01L29/0634 ,  H01L29/0878 ,  H01L29/0886 ,  H01L29/66712 ,  H01L29/7811 ,  H01L29/8611

Abstract: Properties of a semiconductor device are improved. A semiconductor device having a superjunction structure, in which p-type column regions and n-type column regions are periodically arranged, is configured as follows. Each n-type column region has a vertical section including an n-type epitaxial layer located between trenches and a tapered embedded n-type epitaxial film disposed on a side face of the trench. Each p-type column region includes an embedded p-type epitaxial film disposed within the trench. The tapered embedded n-type epitaxial film is thus provided on the sidewall of the trench in which the p-type column region is to be disposed, thereby the p-type column region is allowed to have an inverted trapezoidal shape, leading to an increase in margin for a variation in concentration of a p-type impurity in the p-type column region. On resistance can be reduced by lateral diffusion of an n-type impurity (for example, As).

公开(公告)号：US20130189819A1

公开(公告)日：2013-07-25

申请号：US13742489

申请日：2013-01-16

Applicant: Renesas Electronics Corporation

Inventor： Satoshi EGUCHI ,  Yuya ABIKO ,  Junichi KOGURE

IPC: H01L29/66

CPC classification number: H01L29/7802 ,  H01L21/02639 ,  H01L21/26506 ,  H01L21/26566 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/161 ,  H01L29/165 ,  H01L29/41766 ,  H01L29/66712 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7813 ,  H01L29/7842 ,  H01L29/7848

Abstract: In the manufacturing steps of a super-junction power MOSFET having a drift region having a super junction structure, after the super junction structure is formed, introduction of a body region and the like and heat treatment related thereto are typically performed. However, in the process thereof, a dopant in each of P-type column regions and the like included in the super junction structure is diffused to result in a scattered dopant profile. This causes problems such as degradation of a breakdown voltage when a reverse bias voltage is applied between a drain and a source and an increase in ON resistance. According to the present invention, in a method of manufacturing a silicon-based vertical planar power MOSFET, a body region forming a channel region is formed by selective epitaxial growth.

Abstract translation: 在具有超结结构的漂移区域的超结功率MOSFET的制造步骤中，在形成超结结构之后，通常进行体区等的引入和与其相关的热处理。 然而，在其过程中，包含在超结结构中的每个P型列区域等中的掺杂剂被扩散以产生散射掺杂剂分布。 这导致了当在漏极和源极之间施加反向偏置电压和导通电阻增加时诸如击穿电压劣化的问题。 根据本发明，在制造硅基垂直平面功率MOSFET的方法中，通过选择性外延生长形成形成沟道区的体区。

公开(公告)号：US20230077367A1

公开(公告)日：2023-03-16

申请号：US18057330

申请日：2022-11-21

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yasuhiro OKAMOTO ,  Nobuo MACHIDA ,  Koichi ARAI ,  Kenichi HISADA ,  Yasunori YAMASHITA ,  Satoshi EGUCHI ,  Hironobu MIYAMOTO ,  Atsushi SAKAI ,  Katsumi EIKYU

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/36 ,  H01L29/66 ,  H01L21/02 ,  H01L21/04 ,  H01L29/10 ,  H01L29/08 ,  H01L29/16

Abstract: A drift layer is formed over a semiconductor substrate which is an SiC substrate. The drift layer includes first to third n-type semiconductor layers and a p-type impurity region. Herein, an impurity concentration of the second n-type semiconductor layer is higher than an impurity concentration of the first n-type semiconductor layer and an impurity concentration of the third n-type semiconductor layer. Also, in plan view, the second semiconductor layer located between the p-type impurity regions adjacent to each other overlaps with at least a part of a gate electrode formed in a trench.

公开(公告)号：US20180012959A1

公开(公告)日：2018-01-11

申请号：US15700669

申请日：2017-09-11

Applicant: Renesas Electronics Corporation

Inventor： Akio ICHIMURA ,  Satoshi EGUCHI ,  Tetsuya IIDA ,  Yuya ABIKO

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L29/40 ,  H01L29/10 ,  H01L29/417

CPC classification number: H01L29/0634 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/41766 ,  H01L29/66712 ,  H01L29/66727 ,  H01L29/7811

Abstract: A super junction structure having a high aspect ratio is formed. An epitaxial layer is dividedly formed in layers using the trench fill process, and when each of the layers has been formed, trenches are formed in that layer. For example, when a first epitaxial layer has been formed, first trenches are formed in the epitaxial layer. Subsequently, when a second epitaxial layer has been formed, second trenches are formed in the epitaxial layer. Subsequently, when a third epitaxial layer has been formed, third trenches are formed in the third epitaxial layer.

公开(公告)号：US20170154984A1

公开(公告)日：2017-06-01

申请号：US15355469

申请日：2016-11-18

Applicant: Renesas Electronics Corporation

Inventor： Satoshi EGUCHI ,  Hitoshi MATSUURA ,  Yuya ABIKO

IPC: H01L29/739 ,  H01L21/324 ,  H01L29/66 ,  H01L21/265 ,  H01L29/06 ,  H01L29/32

CPC classification number: H01L29/7396 ,  H01L21/265 ,  H01L21/26506 ,  H01L21/324 ,  H01L29/0634 ,  H01L29/0688 ,  H01L29/1095 ,  H01L29/32 ,  H01L29/404 ,  H01L29/66333 ,  H01L29/6634

Abstract: Reduction of power consumption of a semiconductor device is aimed. The semiconductor device includes a cell region where a vertical power MOSFET is formed and an intermediate region surrounding the cell region. In each of the cell region and the intermediate region, a plurality of p-type column regions and a plurality of n-type column regions are alternately formed. The n-type column region arranged in the cell region has a defect region formed therein, whereas the n-type column region arranged in the intermediate region does not have the defect region. A defect density in the n-type column region arranged in the cell region is larger than that in the n-type column region arranged in the intermediate region.