公开(公告)号：US20150115269A1

公开(公告)日：2015-04-30

申请号：US14517646

申请日：2014-10-17

Applicant: Renesas Electronics Corporation

Inventor： Yasushi ISHII ,  Tetsuo Adachi

IPC: H01L21/66 ,  H01L23/00

CPC classification number: H01L22/32 ,  H01L23/3107 ,  H01L23/562 ,  H01L23/585 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/09 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/02166 ,  H01L2224/0345 ,  H01L2224/0361 ,  H01L2224/03622 ,  H01L2224/03831 ,  H01L2224/0392 ,  H01L2224/04042 ,  H01L2224/05552 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05556 ,  H01L2224/05557 ,  H01L2224/05624 ,  H01L2224/0603 ,  H01L2224/06179 ,  H01L2224/09051 ,  H01L2224/32014 ,  H01L2224/32245 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48463 ,  H01L2224/48465 ,  H01L2224/48624 ,  H01L2224/48824 ,  H01L2224/49052 ,  H01L2224/49113 ,  H01L2224/49431 ,  H01L2224/73265 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/10162 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/3512 ,  H01L2924/381 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/20753

Abstract: This invention provides a semiconductor device with improved reliability. A semiconductor chip (semiconductor device) includes a plurality of electrode pads arranged in a plurality of lines extending along a side (chip side) of a perimeter of the semiconductor chip in plan view. Among the electrode pads, the areas of respective electrode pads arranged in a first line along the chip side are smaller than the areas of respective electrode pads arranged in a line located further than the first line from the chip side.

Abstract translation: 本发明提供一种可靠性提高的半导体器件。 半导体芯片（半导体器件）包括布置在平面图中沿着半导体芯片的周边的一侧（芯片侧）延伸的多条线的多个电极焊盘。 在电极焊盘中，沿着芯片侧布置在第一线中的各个电极焊盘的区域小于布置在比芯片侧的第一线更远的线中的各个电极焊盘的区域。

公开(公告)号：US20140035027A1

公开(公告)日：2014-02-06

申请号：US13958574

申请日：2013-08-04

Applicant: Renesas Electronics Corporation

Inventor： Hiraku CHAKIHARA ,  Yasushi ISHII

IPC: H01L29/423 ,  H01L29/792

CPC classification number: H01L21/28273 ,  G11C16/0466 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11573 ,  H01L29/42324 ,  H01L29/42344 ,  H01L29/66833 ,  H01L29/792

Abstract: A lamination pattern having a control gate electrode, a first insulation film thereover, and a second insulation film thereover is formed over a semiconductor substrate. A memory gate electrode is formed adjacent to the lamination pattern. A gate insulation film is formed between the control gate and the semiconductor substrate. A fourth insulation film, including a lamination film of a silicon oxide film, a silicon nitride film, and another silicon oxide film, is formed between the memory gate electrode and the semiconductor substrate and between the lamination pattern and the memory gate electrode. At the sidewall on the side of the lamination pattern adjacent to the memory gate electrode, the first insulation film is retreated from the control gate electrode and the second insulation film, and the upper end corner portion of the control gate electrode is rounded.

Abstract translation: 在半导体衬底上形成具有控制栅电极，其上的第一绝缘膜和其上的第二绝缘膜的叠层图案。 与层压图案相邻地形成存储栅电极。 在控制栅极和半导体衬底之间形成栅极绝缘膜。 在存储栅电极和半导体衬底之间以及叠层图案和存储栅电极之间形成第四绝缘膜，其包括氧化硅膜的叠层膜，氮化硅膜和另一氧化硅膜。 在与存储栅电极相邻的层叠图案侧的侧壁处，第一绝缘膜从控制栅极电极和第二绝缘膜退回，并且控制栅电极的上端角部分被倒圆。

公开(公告)号：US20130334592A1

公开(公告)日：2013-12-19

申请号：US13970703

申请日：2013-08-20

Applicant: Renesas Electronics Corporation

Inventor： Tsutomu OKAZAKI ,  Daisuke OKADA ,  Kyoya NITTA ,  Toshihiro TANAKA ,  Akira KATO ,  Toshikazu MATSUI ,  Yasushi ISHII ,  Digh HISAMOTO ,  Kan YASUI

IPC: H01L29/792

CPC classification number: H01L27/1157 ,  G11C16/0425 ,  H01L21/28282 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/0649 ,  H01L29/4234 ,  H01L29/42344 ,  H01L29/518 ,  H01L29/66833 ,  H01L29/792

Abstract: A semiconductor memory array includes a first nonvolatile memory cell having a first charge storage layer and a first gate electrode and a second nonvolatile memory cell, adjacent to the first memory cell in a first direction, having a second charge storage layer and a second gate electrode. The first and second electrodes extend in a second direction perpendicular to the first direction, the first electrode has a first contact section extending toward the second electrode in the first direction, and the second electrode has a second contact section extending toward the first electrode in the first direction. The first and second contact positions are shifted in the second direction, respectively, and the first electrode and the first contact section are electrically separated from the second electrode and the second contact section.

公开(公告)号：US20130149854A1

公开(公告)日：2013-06-13

申请号：US13662509

申请日：2012-10-28

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yasushi ISHII ,  Hiraku CHAKIHARA ,  Kentaro SAITO

IPC: H01L21/82

CPC classification number: H01L27/088 ,  H01L21/28008 ,  H01L21/82 ,  H01L21/823425 ,  H01L21/823814 ,  H01L21/82385 ,  H01L21/823857 ,  H01L21/823864

Abstract: An improvement is achieved in the manufacturing yield of a semiconductor device including a plurality of field effect transistors having different characteristics over the same substrate. By combining anisotropic dry etching with isotropic wet etching or isotropic dry etching, three types of sidewalls having different sidewall lengths are formed. By reducing the number of anisotropic dry etching steps, in a third n-type MISFET region and a third p-type MISFET region where layout densities are high, it is possible to prevent a semiconductor substrate from being partially cut between n-type gate electrodes adjacent to each other, between the n-type gate electrode and a p-type gate electrode adjacent to each other, and the p-type gate electrodes adjacent to each other.

Abstract translation: 在包括在相同基板上具有不同特性的多个场效应晶体管的半导体器件的制造成品率方面的改进。 通过将各向异性干法蚀刻与各向同性湿蚀刻或各向同性干法蚀刻相结合，形成具有不同侧壁长度的三种类型的侧壁。 通过减少各向异性干蚀刻步骤的数量，在布置密度高的第三n型MISFET区域和第三p型MISFET区域中，可以防止半导体衬底在n型栅极之间被部分切割 彼此相邻的n型栅电极和彼此相邻的p型栅极之间，以及彼此相邻的p型栅电极。

公开(公告)号：US20170229469A1

公开(公告)日：2017-08-10

申请号：US15581576

申请日：2017-04-28

Applicant: Renesas Electronics Corporation

Inventor： Tsutomu OKAZAKI ,  Daisuke OKADA ,  Kyoya NITTA ,  Toshihiro TANAKA ,  Akira KATO ,  Toshikazu MATSUI ,  Yasushi ISHII ,  Digh HISAMOTO ,  Kan YASUI

IPC: H01L27/1157 ,  H01L29/423 ,  H01L21/28 ,  H01L29/792 ,  H01L29/66 ,  H01L27/02 ,  H01L29/51 ,  H01L29/06

CPC classification number: H01L27/1157 ,  G11C16/0425 ,  H01L21/28282 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/0649 ,  H01L29/4234 ,  H01L29/42344 ,  H01L29/518 ,  H01L29/66833 ,  H01L29/792

Abstract: A semiconductor memory array includes a first nonvolatile memory cell having a first charge storage layer and a first gate electrode and a second nonvolatile memory cell, adjacent to the first memory cell in a first direction, having a second charge storage layer and a second gate electrode. The first and second electrodes extend in a second direction perpendicular to the first direction, the first electrode has a first contact section extending toward the second electrode in the first direction, and the second electrode has a second contact section extending toward the first electrode in the first direction. The first and second contact positions are shifted in the second direction, respectively, and the first electrode and the first contact section are electrically separated from the second electrode and the second contact section.

公开(公告)号：US20130234289A1

公开(公告)日：2013-09-12

申请号：US13867213

申请日：2013-04-22

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yoshiyuki KAWASHIMA ,  Koichi TOBA ,  Yasushi ISHII ,  Toshikazu MATSUI ,  Takashi HASHIMOTO

IPC: H01L49/02

CPC classification number: H01L28/60 ,  H01L27/0629 ,  H01L27/0805 ,  H01L27/105 ,  H01L27/10805 ,  H01L27/11526 ,  H01L27/11531 ,  H01L27/11573 ,  H01L28/40

Abstract: In connection with a semiconductor device including a capacitor element there is provided a technique capable of improving the reliability of the capacitor element. A capacitor element is formed in an element isolation region formed over a semiconductor substrate. The capacitor element includes a lower electrode and an upper electrode formed over the lower electrode through a capacitor insulating film. Basically, the lower electrode and the upper electrode are formed from polysilicon films and a cobalt silicide film formed over the surfaces of the polysilicon films. End portions of the cobalt silicide film formed over the upper electrode are spaced apart a distance from end portions of the upper electrode. Besides, end portions of the cobalt silicide film formed over the lower electrode are spaced apart a distance from boundaries between the upper electrode and the lower electrode.

公开(公告)号：US20130164927A1

公开(公告)日：2013-06-27

申请号：US13772470

申请日：2013-02-21

Applicant: Renesas Electronics Corporation

Inventor： Hiraku CHAKIHARA ,  Yasushi ISHII

IPC: H01L29/66

CPC classification number: H01L21/28273 ,  G11C16/0466 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11573 ,  H01L29/42324 ,  H01L29/42344 ,  H01L29/66833 ,  H01L29/792

Abstract: A lamination pattern having a control gate electrode, a first insulation film thereover, and a second insulation film thereover is formed over a semiconductor substrate. A memory gate electrode is formed adjacent to the lamination pattern. A gate insulation film is formed between the control gate and the semiconductor substrate. A fourth insulation film, including a lamination film of a silicon oxide film, a silicon nitride film, and another silicon oxide film, is formed between the memory gate electrode and the semiconductor substrate and between the lamination pattern and the memory gate electrode. At the sidewall on the side of the lamination pattern adjacent to the memory gate electrode, the first insulation film is retreated from the control gate electrode and the second insulation film, and the upper end corner portion of the control gate electrode is rounded.

Abstract translation: 在半导体衬底上形成具有控制栅电极，其上的第一绝缘膜和其上的第二绝缘膜的叠层图案。 与层压图案相邻地形成存储栅电极。 在控制栅极和半导体衬底之间形成栅极绝缘膜。 在存储栅电极和半导体衬底之间以及叠层图案和存储栅电极之间形成第四绝缘膜，其包括氧化硅膜的叠层膜，氮化硅膜和另一氧化硅膜。 在与存储栅电极相邻的层叠图案侧的侧壁处，第一绝缘膜从控制栅极电极和第二绝缘膜退回，并且控制栅电极的上端角部分被倒圆。

公开(公告)号：US20130126960A1

公开(公告)日：2013-05-23

申请号：US13740045

申请日：2013-01-11

Applicant: Renesas Electronics Corporation

Inventor： Hiraku CHAKIHARA ,  Yasushi ISHII

IPC: H01L29/792

CPC classification number: H01L27/11575 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/823443 ,  H01L21/823462 ,  H01L21/823835 ,  H01L27/0922 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11546 ,  H01L27/11548 ,  H01L27/11565 ,  H01L27/11568 ,  H01L28/40 ,  H01L29/0649 ,  H01L29/42324 ,  H01L29/42328 ,  H01L29/4234 ,  H01L29/42344 ,  H01L29/4975 ,  H01L29/6653 ,  H01L29/66659 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7835 ,  H01L29/7881 ,  H01L29/792

Abstract: Technique of improving a manufacturing yield of a semiconductor device including a non-volatile memory cell in a split-gate structure is provided. A select gate electrode of a CG shunt portion is formed so that a second height d2 from the main surface of the semiconductor substrate of the select gate electrode of the CG shunt portion positioned in the feeding region is lower than a first height d1 of the select gate electrode from the main surface of the semiconductor substrate in a memory cell forming region.

Abstract translation: 提供了一种提高包括分离栅结构中的非易失性存储单元的半导体器件的制造成品率的技术。 形成CG分流部的选择栅电极，使得位于馈电区域的CG分流部的选择栅电极的半导体衬底的主表面的第二高度d2低于选择区域的第一高度d1 栅极电极从存储单元形成区域中的半导体衬底的主表面。