公开(公告)号：US20190317276A1

公开(公告)日：2019-10-17

申请号：US16370409

申请日：2019-03-29

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Tetsuya IIDA ,  Yasutaka NAKASHIBA

IPC: G02B6/12 ,  H01L31/12 ,  H01L31/0232 ,  H01L31/02 ,  H01L31/18 ,  H01S5/022

Abstract: According to the present invention, a first semiconductor chip includes a semiconductor substrate, an optical waveguide formed on an upper surface of the semiconductor substrate, and a concave portion formed in the semiconductor substrate in a region that differs from a region in which the optical waveguide is formed. A second semiconductor chip includes a compound semiconductor substrate, and a light emitting unit formed on an upper surface of the compound semiconductor substrate and emitting a laser beam. The second semiconductor chip is mounted in the concave portion of the first semiconductor chip, and a pedestal which is an insulating film is formed between a bottom surface of the concave portion and a back surface of the compound semiconductor substrate.

公开(公告)号：US20180341165A1

公开(公告)日：2018-11-29

申请号：US15965900

申请日：2018-04-28

Applicant: Renesas Electronics Corporation

Inventor： Shinichi WATANUKI ,  Yasutaka NAKASHIBA ,  Masaru WAKABAYASHI

IPC: G02F1/225

CPC classification number: G02F1/2257 ,  G02F2001/212 ,  G02F2201/063

Abstract: In a semiconductor device connected to a first optical waveguide, a phase modulation unit, and a second optical waveguide in this order and having an optical modulator guiding light in a first direction, the phase modulation unit includes: a semiconductor layer whose length in the first direction is larger than a width in a second direction orthogonal to the first direction and which is made of monocrystalline silicon; a core part serving as an optical waveguide region formed on the semiconductor layer, and extending in the first direction; a pair of slab parts arranged on both sides of the core part in the second direction; a first electrode coupled with one of the slab parts; and a second electrode coupled with the other of the slab parts. The core part has a p type semiconductor region and an n type semiconductor region extending in the first direction, and the second direction coincides with a crystal orientation of the semiconductor layer.

公开(公告)号：US20170023732A1

公开(公告)日：2017-01-26

申请号：US15186528

申请日：2016-06-19

Applicant: Renesas Electronics Corporation

Inventor： Shinichi WATANUKI ,  Yasutaka NAKASHIBA

IPC: G02B6/12 ,  G02B6/42

CPC classification number: G02B6/428 ,  G02B6/43 ,  G02B2006/12061

Abstract: An interposer includes a plurality of identical functional blocks arranged in the x direction, for example, and the functional blocks include a first region mounting a semiconductor chip, a second region mounting a light emitting element chip, a third region mounting a light receiving element chip, and a plurality of silicon waveguides. Then, the second and third regions are arranged between the first region and a first side along the x direction of the interposer. In addition, the plurality of silicon waveguides are arranged between the second region and the first side, and between the third region and the first side, extending from the second region toward the first side and from the third region toward the first side and are not formed between the functional blocks adjacent in the x direction.

Abstract translation: 插入器包括例如沿x方向布置的多个相同的功能块，功能块包括安装半导体芯片的第一区域，安装发光元件芯片的第二区域，安装光接收元件芯片的第三区域 ，以及多个硅波导。 然后，第二区域和第三区域沿着插入件的x方向布置在第一区域和第一侧之间。 此外，多个硅波导布置在第二区域和第一侧之间以及第三区域和第一侧之间，从第二区域朝向第一侧和从第三区域朝向第一侧延伸，并且不是 形成在x方向相邻的功能块之间。

公开(公告)号：US20160204099A1

公开(公告)日：2016-07-14

申请号：US14931991

申请日：2015-11-04

Applicant: Renesas Electronics Corporation

Inventor： Tohru KAWAI ,  Yasutaka NAKASHIBA ,  Yutaka AKIYAMA

IPC: H01L27/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/739 ,  H01L29/78

CPC classification number: H01L29/7813 ,  H01L23/4952 ,  H01L23/49562 ,  H01L23/5223 ,  H01L24/05 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L27/0629 ,  H01L27/0733 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/4236 ,  H01L29/66333 ,  H01L29/66348 ,  H01L29/66712 ,  H01L29/66734 ,  H01L29/7395 ,  H01L29/7397 ,  H01L29/7803 ,  H01L2224/05624 ,  H01L2224/0603 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/48464 ,  H01L2224/49111 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00012

Abstract: Performance of a semiconductor device is improved without increasing an area size of a semiconductor chip. For example, a source electrode of a power transistor and an upper electrode of a capacitor element have an overlapping portion. In other word, the upper electrode of the capacitor element is formed over the source electrode of the power transistor through a capacitor insulating film. That is, the power transistor and the capacitor element are arranged in a laminated manner in a thickness direction of the semiconductor chip. As a result, it becomes possible to add a capacitor element to be electrically coupled to the power transistor while suppressing an increase in planar size of the semiconductor chip.

Abstract translation: 提高半导体器件的性能而不增加半导体芯片的面积尺寸。 例如，功率晶体管的源电极和电容器元件的上电极具有重叠部分。 换句话说，电容器元件的上电极通过电容器绝缘膜形成在功率晶体管的源极上。 也就是说，功率晶体管和电容器元件以半导体芯片的厚度方向层叠的方式配置。 结果，可以在抑制半导体芯片的平面尺寸的增加的同时添加电耦合到功率晶体管的电容器元件。

公开(公告)号：US20150325696A1

公开(公告)日：2015-11-12

申请号：US14804819

申请日：2015-07-21

Applicant: Renesas Electronics Corporation

Inventor： Akihiro SHIMOMURA ,  Yutaka AKIYAMA ,  Saya SHIMOMURA ,  Yasutaka NAKASHIBA

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/40 ,  H01L29/423

CPC classification number: H01L29/7827 ,  H01L29/0623 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/42372 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/7397 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/8083

Abstract: A semiconductor device including a first conductor layer, a second conductor layer formed over the first conductor layer, a third conductor layer formed over the second conductor layer, a gate trench which passes through the third conductor layer and is formed in the second conductor layer, a first insulating film formed on an inner wall of the gate trench, a second insulating film formed on the inner wall of the gate trench, a first buried conductor layer formed in the gate trench, a gate electrode formed in the gate trench, a fourth conductor layer of the second conductivity type formed on a lower end of the first buried conductor layer and a lower end of the gate trench, and a fifth conduction layer of the first conductivity type formed over the third conductor layer. The first insulating film is thicker than the second insulating film.

Abstract translation: 一种半导体器件，包括第一导体层，形成在第一导体层上的第二导体层，形成在第二导体层上的第三导体层，通过第三导体层并形成在第二导体层中的栅极沟槽， 形成在栅极沟槽的内壁上的第一绝缘膜，形成在栅极沟槽的内壁上的第二绝缘膜，形成在栅极沟槽中的第一掩埋导体层，形成在栅极沟槽中的栅电极，第四绝缘膜 在第一掩埋导体层的下端形成的第二导电类型的导体层和栅极沟槽的下端，以及形成在第三导体层上的第一导电类型的第五导电层。 第一绝缘膜比第二绝缘膜厚。

公开(公告)号：US20150179572A1

公开(公告)日：2015-06-25

申请号：US14638287

申请日：2015-03-04

Applicant: Renesas Electronics Corporation

Inventor： Yasutaka NAKASHIBA

IPC: H01L23/522 ,  H01L23/528 ,  H01L49/02

CPC classification number: H01L23/5227 ,  H01L23/50 ,  H01L23/528 ,  H01L23/5383 ,  H01L24/48 ,  H01L24/49 ,  H01L27/04 ,  H01L28/10 ,  H01L2224/05553 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/4813 ,  H01L2224/48137 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/12041 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/85399 ,  H01L2224/05599

Abstract: A semiconductor device sends and receives electrical signals. The semiconductor device includes a first substrate provided with a first circuit region containing a first circuit; a multi-level interconnect structure provided on the first substrate; a first inductor provided in the multi-level interconnect structure so as to include the first circuit region; and a second inductor provided in the multi-level interconnect structure so as to include the first circuit region, wherein one of the first inductor and the second inductor is connected to the first circuit and the other of the first inductor and the second inductor is connected to a second circuit.

Abstract translation: 半导体器件发送和接收电信号。 半导体器件包括：第一衬底，设置有包含第一电路的第一电路区域; 设置在所述第一基板上的多级互连结构; 设置在所述多电平互连结构中以便包括所述第一电路区域的第一电感器; 以及设置在所述多电平互连结构中的第二电感器，以便包括所述第一电路区域，其中所述第一电感器和所述第二电感器中的一个连接到所述第一电路，并且所述第一电感器和所述第二电感器中的另一个被连接 到第二电路。

公开(公告)号：US20150035080A1

公开(公告)日：2015-02-05

申请号：US14339013

申请日：2014-07-23

Applicant: Renesas Electronics Corporation

Inventor： Akira Matsumoto ,  Yoshinao MIURA ,  Yasutaka NAKASHIBA

IPC: H01L27/088 ,  H01L23/50 ,  H01L27/02

CPC classification number: H01L23/49562 ,  H01L23/4824 ,  H01L23/485 ,  H01L23/492 ,  H01L23/49503 ,  H01L23/4952 ,  H01L23/49548 ,  H01L23/49575 ,  H01L23/50 ,  H01L23/528 ,  H01L23/5283 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L27/0203 ,  H01L27/0605 ,  H01L27/088 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/41758 ,  H01L29/4236 ,  H01L29/7786 ,  H01L29/7787 ,  H01L29/78 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/45014 ,  H01L2224/451 ,  H01L2224/4805 ,  H01L2224/4813 ,  H01L2224/48177 ,  H01L2224/48247 ,  H01L2224/49113 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/1033 ,  H01L2924/10344 ,  H01L2924/13064 ,  H01L2924/30101 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: Disclosed is a semiconductor device in which a resistance component resulting from wiring is reduced. A plurality of transistor units are arranged side by side in a first direction (Y direction in the view), each of which has a plurality of transistors. The gate electrodes of the transistors extend in the first direction. First source wiring extends between first transistor unit and second transistor unit, and first drain wiring extends between the second transistor unit and third transistor unit. Second drain wiring extends on the side of the first transistor unit opposite to the side where the first source wiring extends, and second source wiring extends on the side of the third transistor unit opposite to the side where the second drain wiring extends.

Abstract translation: 公开了一种半导体器件，其中由布线产生的电阻分量减小。 多个晶体管单元沿着第一方向（视图中的Y方向）并排布置，每个晶体管单元具有多个晶体管。 晶体管的栅电极沿第一方向延伸。 第一源极布线在第一晶体管单元和第二晶体管单元之间延伸，并且第一漏极布线在第二晶体管单元和第三晶体管单元之间延伸。 第二漏极布线在第一晶体管单元的与第一源极布线延伸的一侧相反的一侧延伸，并且第二源极布线在与第二漏极布线延伸的一侧相反的一侧延伸。

公开(公告)号：US20140284709A1

公开(公告)日：2014-09-25

申请号：US14204145

申请日：2014-03-11

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Akihiro SHIMOMURA ,  Yutaka AKIYAMA ,  Saya SHIMOMURA ,  Yasutaka NAKASHIBA

IPC: H01L29/78 ,  H01L29/423

CPC classification number: H01L29/7827 ,  H01L29/0623 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/42372 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/7397 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/8083

Abstract: A buried layer of a second conductivity type and a lower layer of a second conductivity type are formed in a drift layer. A boundary insulating film is formed in the boundary between the lateral portion of the buried layer of a second conductivity type and the drift layer. The lower layer of a second conductivity type is in contact with the lower end of the buried layer of a second conductivity type and the lower end of the boundary insulating film. The buried layer of a second conductivity type is electrically connected to a source electrode. A high-concentration layer of a second conductivity type is formed in the surface layer of the buried layer of a second conductivity type.

Abstract translation: 在漂移层中形成第二导电类型的掩埋层和第二导电类型的下层。 边界绝缘膜形成在第二导电类型的掩埋层的横向部分与漂移层之间的边界中。 第二导电类型的下层与第二导电类型的掩埋层的下端和边界绝缘膜的下端接触。 第二导电类型的掩埋层与源电极电连接。 在第二导电类型的掩埋层的表面层中形成第二导电类型的高浓度层。

公开(公告)号：US20140061934A1

公开(公告)日：2014-03-06

申请号：US14075513

申请日：2013-11-08

Applicant: Renesas Electronics Corporation

Inventor： Masayuki FURUMIYA ,  Yasutaka NAKASHIBA ,  Akira TANABE

IPC: H01L23/48 ,  H01L23/528

CPC classification number: H01L23/481 ,  H01L21/823871 ,  H01L23/5225 ,  H01L23/528 ,  H01L23/5286 ,  H01L2223/6627 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/1903 ,  H01L2924/3011 ,  H01L2924/00

Abstract: A semiconductor device with a transistor region has a first conductor pattern formed within a multilayer interconnect structure positioned under a signal line and above the transistor region. The first conductor pattern is coupled to ground or a power supply and overlaps the transistor region. The signal line overlaps the first conductor pattern.

Abstract translation: 具有晶体管区域的半导体器件具有形成在位于信号线下方并位于晶体管区域之上的多层互连结构内的第一导体图案。 第一导体图案耦合到地或电源并与晶体管区重叠。 信号线与第一导体图案重叠。

公开(公告)号：US20130093096A1

公开(公告)日：2013-04-18

申请号：US13708207

申请日：2012-12-07

Applicant: Renesas Electronics Corporation

Inventor： Masayuki FURUMIYA ,  Yasutaka NAKASHIBA ,  Akira TANABE

IPC: H01L23/48

CPC classification number: H01L23/481 ,  H01L21/823871 ,  H01L23/5225 ,  H01L23/528 ,  H01L23/5286 ,  H01L2223/6627 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/1903 ,  H01L2924/3011 ,  H01L2924/00

Abstract: A semiconductor device with a transistor region has a first conductor pattern formed within a multilayer interconnect structure positioned under a signal line and above the transistor region. The first conductor pattern is coupled to ground or a power supply and overlaps the transistor region. The signal line overlaps the first conductor pattern.

Abstract translation: 具有晶体管区域的半导体器件具有形成在位于信号线下方并位于晶体管区域之上的多层互连结构内的第一导体图案。 第一导体图案耦合到地或电源并与晶体管区重叠。 信号线与第一导体图案重叠。