公开(公告)号：US20050277266A1

公开(公告)日：2005-12-15

申请号：US10710034

申请日：2004-06-14

申请人： Edward Cooney ,  Vincent McGahay ,  Thomas Shaw ,  Anthony Stamper ,  Matthew Colburn

发明人： Edward Cooney ,  Vincent McGahay ,  Thomas Shaw ,  Anthony Stamper ,  Matthew Colburn

IPC分类号： C23C14/00 ,  C23C14/32 ,  H01L21/30 ,  H01L21/302 ,  H01L21/311 ,  H01L21/46 ,  H01L21/461 ,  H01L21/768 ,  H01L21/78

CPC分类号： H01L21/76829 ,  H01L21/31144 ,  H01L21/76828 ,  H01L21/78

摘要： The present invention relates to a process for improved interfacial adhesion of dielectrics using patterned roughing. Improved adhesion strength between layers and substrates can be achieved through increasing the roughness of the interface between the materials. Roughness may including any disturbance of an otherwise generally smooth surface, such as grooves, indents, holes, trenches, and/or the like. Roughing on the interface may be achieved by depositing a material on a surface of the substrate to act as a mask and then using an etching process to induce the roughness. The material, acting as a mask, allows etching to occur on a fine, or sub-miniature, scale below the Scale achieved with a conventional photo mask and lithography to achieve the required pattern roughing. Another material is then deposited on the roughened surface of the substrate, filling in the roughing and adhering to the substrate.

摘要翻译： 本发明涉及使用图案化粗糙化改善电介质的界面粘附的方法。 可以通过增加材料之间的界面的粗糙度来实现层和基底之间的改善的粘附强度。 粗糙度可能包括任何干扰通常平滑的表面，如凹槽，凹痕，孔，沟槽等。 可以通过在衬底的表面上沉积材料作为掩模，然后使用蚀刻工艺来引起粗糙度来实现界面上的粗加工。 用作掩模的材料允许蚀刻在以常规光掩模和光刻实现的规模以下的精细或次微小尺度上发生，以实现所需的图案粗糙化。 然后将另一种材料沉积在基底的粗糙表面上，填充粗加工并粘附到基底上。

公开(公告)号：US20050167838A1

公开(公告)日：2005-08-04

申请号：US10707996

申请日：2004-01-30

申请人： Daniel Edelstein ,  Matthew Colburn ,  Edward Cooney ,  Timothy Dalton ,  John Fitzsimmons ,  Jeffrey Gambino ,  Elbert Huang ,  Michael Lane ,  Vincent McGahay ,  Lee Nicholson ,  Satyanarayana Nitta ,  Sampath Purushothaman ,  Sujatha Sankaran ,  Thomas Shaw ,  Andrew Simon ,  Anthony Stamper

发明人： Daniel Edelstein ,  Matthew Colburn ,  Edward Cooney ,  Timothy Dalton ,  John Fitzsimmons ,  Jeffrey Gambino ,  Elbert Huang ,  Michael Lane ,  Vincent McGahay ,  Lee Nicholson ,  Satyanarayana Nitta ,  Sampath Purushothaman ,  Sujatha Sankaran ,  Thomas Shaw ,  Andrew Simon ,  Anthony Stamper

IPC分类号： H01L21/033 ,  H01L21/302 ,  H01L21/311 ,  H01L21/4763 ,  H01L21/768 ,  H01L23/48 ,  H01L23/522 ,  H01L23/532 ,  H01L29/40

CPC分类号： B82Y30/00 ,  H01L21/0332 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/7682 ,  H01L21/76829 ,  H01L23/5222 ,  H01L23/53295 ,  H01L2924/0002 ,  Y10S438/947 ,  H01L2924/00

摘要： A method for manufacturing a structure includes providing a structure having an insulator layer with at least one interconnect and forming a sub lithographic template mask on the insulator layer. A selective etching step is used for etching the insulator layer through the sub lithographic template mask to form sub lithographic features near the at least one interconnect. A supra lithographic blocking mask may also be utilized. In another aspect, the method includes forming pinch off sections of sub lithographic size formed in a capping layer on the insulator layer. A semiconductor structure includes an insulator layer having at least one interconnect feature and at least one column formed in the insulator layer. A plurality of sub lithographic features formed on a top portion of the insulator layer and communicating with the at least one column is also provided. The plurality of sub lithographic features have a cross section or diameter less than any of the at least one column. A gap may be prohibited from forming on or near scribe lanes and vias

摘要翻译： 一种制造结构的方法包括提供具有至少一个互连的绝缘层的结构，并在绝缘体层上形成次光刻模板掩模。 选择性蚀刻步骤用于通过子光刻模板掩模蚀刻绝缘体层，以在至少一个互连附近形成亚光刻特征。 还可以使用超光刻阻挡掩模。 另一方面，该方法包括形成在绝缘体层上的覆盖层中形成的亚光刻尺寸的夹断部分。 半导体结构包括具有至少一个互连特征的绝缘体层和形成在绝缘体层中的至少一个列。 还提供了形成在绝缘体层的顶部并与至少一个柱连通的多个次级光刻特征。 所述多个亚光刻特征具有小于或小于所述至少一列中的任何一个的横截面或直径。 可能禁止在划线车道和通道上或附近形成间隙

公开(公告)号：US20080020546A1

公开(公告)日：2008-01-24

申请号：US11862706

申请日：2007-09-27

申请人： Edward COONEY ,  Vincent McGahay ,  Thomas Shaw ,  Anthony Stamper ,  Matthew Colburn

发明人： Edward COONEY ,  Vincent McGahay ,  Thomas Shaw ,  Anthony Stamper ,  Matthew Colburn

IPC分类号： H01L21/475 ,  H01L21/302 ,  H01L21/32 ,  H01L21/467

CPC分类号： H01L21/76829 ,  H01L21/31144 ,  H01L21/76828 ,  H01L21/78

摘要： The present invention relates to a process for improved interfacial adhesion of dielectrics using patterned roughing. Improved adhesion strength between layers and substrates can be achieved through increasing the roughness of the interface between the materials. Roughness may including any disturbance of an otherwise generally smooth surface, such as grooves, indents, holes, trenches, and/or the like. Roughing on the interface may be achieved by depositing a material on a surface of the substrate to act as a mask and then using an etching process to induce the roughness. The material, acting as a mask, allows etching to occur on a fine, or sub-miniature, scale below the Scale achieved with a conventional photo mask and lithography to achieve the required pattern roughing. Another material is then deposited on the roughened surface of the substrate, filling in the roughing and adhering to the substrate.

摘要翻译： 本发明涉及使用图案化粗糙化改善电介质的界面粘附的方法。 可以通过增加材料之间的界面的粗糙度来实现层和基底之间的改善的粘附强度。 粗糙度可能包括任何干扰通常平滑的表面，如凹槽，凹痕，孔，沟槽等。 可以通过在衬底的表面上沉积材料作为掩模，然后使用蚀刻工艺来引起粗糙度来实现界面上的粗加工。 用作掩模的材料允许蚀刻在以常规光掩模和光刻实现的规模以下的精细或次微小尺度上发生，以实现所需的图案粗糙化。 然后将另一种材料沉积在基底的粗糙表面上，填充粗加工并粘附到基底上。

公开(公告)号：US20060091559A1

公开(公告)日：2006-05-04

申请号：US10981233

申请日：2004-11-04

申请人： Son Nguyen ,  Michael Lane ,  Stephen Gates ,  Xiao Liu ,  Vincent McGahay ,  Sanjay Mehta ,  Thomas Shaw

发明人： Son Nguyen ,  Michael Lane ,  Stephen Gates ,  Xiao Liu ,  Vincent McGahay ,  Sanjay Mehta ,  Thomas Shaw

IPC分类号： H01L21/4763 ,  H01L23/52 ,  H01L21/31

CPC分类号： H01L21/3148 ,  H01L21/02126 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/3122 ,  H01L21/76807 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76832 ,  H01L23/53295 ,  H01L2924/0002 ,  Y10T428/24802 ,  H01L2924/00

摘要： The present invention provides a hardmask that is located on a surface of a low k dielectric material having at least one conductive feature embedded therein. The hardmask includes a lower region of a hermetic oxide material located adjacent to the low k dielectric material and an upper region comprising atoms of Si, C and H located above the hermetic oxide material. The present invention also provides a method of fabricating the inventive hardmask as well as a method to form an interconnect structure containing the same.

公开(公告)号：US20060012014A1

公开(公告)日：2006-01-19

申请号：US10891605

申请日：2004-07-15

申请人： Shyng-Tsong Chen ,  Stefanie Chiras ,  Michael Lane ,  Qinghuang Lin ,  Robert Rosenberg ,  Thomas Shaw ,  Terry Spooner

发明人： Shyng-Tsong Chen ,  Stefanie Chiras ,  Michael Lane ,  Qinghuang Lin ,  Robert Rosenberg ,  Thomas Shaw ,  Terry Spooner

IPC分类号： H01L21/44

CPC分类号： H01L21/76801 ,  H01L21/76807 ,  H01L21/76829 ,  H01L21/76832

摘要： The present invention provides a plastically and/or viscoelastically deformable layer that can be used in conjunction with a low-k dielectric (k of less than 4.0) to provide an electronic semiconductor structure having improved reliability. The deformable layer can be incorporated into various points within an electronic structure to dissipate energy within the structure that may cause the low-k dielectric material to crack or delaminate therefrom. Moreover, the presence of the deformable layer with the electronic structure improves the overall strength of the resultant structure.

摘要翻译： 本发明提供了可以与低k电介质（k小于4.0）结合使用的塑性和/或粘弹性变形层，以提供具有改进的可靠性的电子半导体结构。 可变形层可以结合到电子结构内的各个点中以消散结构内的能量，这可能导致低k电介质材料从其中破裂或分层。 此外，具有电子结构的可变形层的存在提高了所得结构的总体强度。

公开(公告)号：US20080044668A1

公开(公告)日：2008-02-21

申请号：US11034479

申请日：2005-01-13

申请人： Christos Dimitrakopoulos ,  Stephen Gates ,  Alfred Grill ,  Michael Lane ,  Eric Liniger ,  Xiao Liu ,  Son Nguyen ,  Deborah Neumayer ,  Thomas Shaw

发明人： Christos Dimitrakopoulos ,  Stephen Gates ,  Alfred Grill ,  Michael Lane ,  Eric Liniger ,  Xiao Liu ,  Son Nguyen ,  Deborah Neumayer ,  Thomas Shaw

IPC分类号： B32B9/04 ,  B32B13/04

CPC分类号： H01L21/76834 ,  C23C16/30 ,  C23C16/56 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02274 ,  H01L21/02282 ,  H01L21/02348 ,  H01L21/3105 ,  H01L21/31058 ,  H01L21/31633 ,  H01L21/76801 ,  H01L21/76825 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76832 ,  Y10T428/249953 ,  Y10T428/249969 ,  Y10T428/249979

摘要： A method for forming a ultralow dielectric constant layer with controlled biaxial stress is described incorporating the steps of forming a layer containing Si, C, O and H by one of PECVD and spin-on coating and curing the film in an environment containing very low concentrations of oxygen and water each less than 10 ppm. A material is also described by using the method with a dielectric constant of not more than 2.8. The invention overcomes the problem of forming films with low biaxial stress less than 46 MPa.

摘要翻译： 描述了形成具有受控双轴应力的超低介电常数层的方法，其包括以下步骤：通过PECVD和旋涂方法之一形成包含Si，C，O和H的层，并在含有非常低的浓度的环境中固化该膜 的氧和水各自小于10ppm。 还通过使用介电常数不大于2.8的方法描述材料。 本发明克服了低双轴应力低于46MPa的薄膜形成问题。

公开(公告)号：US20070164337A1

公开(公告)日：2007-07-19

申请号：US11687000

申请日：2007-03-16

申请人： James Adkisson ,  Charles Black ,  Alfred Grill ,  Randy Mann ,  Deborah Neumayer ,  Wilbur Pricer ,  Katherine Saenger ,  Thomas Shaw

发明人： James Adkisson ,  Charles Black ,  Alfred Grill ,  Randy Mann ,  Deborah Neumayer ,  Wilbur Pricer ,  Katherine Saenger ,  Thomas Shaw

IPC分类号： H01L29/94

CPC分类号： H01L28/55 ,  H01L27/0629 ,  H01L27/11502 ,  H01L27/11507 ,  Y10S438/977

摘要： A method of forming an integrated ferroelectric/CMOS structure which effectively separates incompatible high temperature deposition and annealing processes is provided. The method of the present invention includes separately forming a CMOS structure and a ferroelectric delivery wafer. These separate structures are then brought into contact with each and the ferroelectric film of the delivery wafer is bonded to the upper conductive electrode layer of the CMOS structure by using a low temperature anneal step. A portion of the delivery wafer is then removed providing an integrated FE/CMOS structure wherein the ferroelectric capacitor is formed on top of the CMOS structure. The capacitor is in contact with the transistor of the CMOS structure through all the wiring levels of the CMOS structure.

摘要翻译： 提供了一种形成集成的铁电/ CMOS结构的方法，其有效地分离不兼容的高温沉积和退火工艺。 本发明的方法包括分别形成CMOS结构和铁电输送晶片。 然后使这些分离的结构与每个结构接触，并且通过使用低温退火步骤将输送晶片的铁电体膜结合到CMOS结构的上导电电极层。 然后去除输送晶片的一部分，提供集成的FE / CMOS结构，其中铁电电容器形成在CMOS结构的顶部。 电容器通过CMOS结构的所有布线级与CMOS结构的晶体管接触。

公开(公告)号：US20070117408A1

公开(公告)日：2007-05-24

申请号：US11164425

申请日：2005-11-22

申请人： Son Nguyen ,  Thomas Shaw

发明人： Son Nguyen ,  Thomas Shaw

IPC分类号： H01L21/469

CPC分类号： H01L21/31633 ,  C23C16/401 ,  C23C16/56 ,  H01L21/02126 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/02337

摘要： A method for reducing the tensile stress of a low-k dielectric layer includes depositing an organosilicate layer on a substrate, the layer having an initial tensile stress value associated therewith. The layer is annealed in a reactive environment at a temperature and for a duration selected to result in the layer having a reduced tensile stress value with respect the initial tensile stress value following the completion of the annealing.

摘要翻译： 降低低k电介质层的拉伸应力的方法包括在基底上沉积有机硅酸盐层，该层具有与其相关联的初始拉伸应力值。 该层在反应环境中在选定的温度和持续时间内在反应性环境中退火，导致该层在退火完成后相对于初始拉伸应力值具有降低的拉伸应力值。

公开(公告)号：US20060084919A1

公开(公告)日：2006-04-20

申请号：US10969128

申请日：2004-10-18

申请人： Thomas Shaw ,  Gary Wood ,  Mark Small

发明人： Thomas Shaw ,  Gary Wood ,  Mark Small

IPC分类号： A61M5/00 ,  A61M5/315

CPC分类号： A61M5/31535 ,  A61M5/3234 ,  A61M5/508 ,  A61M2205/582

摘要： A syringe configured with a limited maximum usable capacity. The syringe of the invention desirably has a retractable needle to prevent reuse. In the preferred embodiment, a dose-limiting structure includes a stop-ring member on the head of the plunger that abuts a constriction in the housing when the plunger is moved away from the needle to prevent the further rearward movement of the plunger. Preferably, the syringe of the invention is configured such that a user is tactilely signaled when the plunger has reached a position corresponding to a nominal fixed-dose. If the user attempts to force the stop-ring member beyond the constriction, the plunger seal is stripped off or removed from the plunger head and the syringe rendered inoperable. The features of the invention can also be applied to a nonretracting syringe.

摘要翻译： 注射器配置有限的最大可用容量。 本发明的注射器理想地具有可缩回的针以防止重复使用。 在优选实施例中，剂量限制结构包括在柱塞的头部上的止动环构件，其在柱塞远离针头移动时抵靠壳体中的收缩部，以防止柱塞进一步向后移动。 优选地，本发明的注射器被构造成使得当柱塞已经达到对应于标称固定剂量的位置时，用户被触觉地发出信号。 如果用户试图迫使止动环构件超出收缩部，则活塞密封件被从柱塞头剥离或移除，注射器不可操作。 本发明的特征也可以应用于非拉伸注射器。

公开(公告)号：US20050196917A1

公开(公告)日：2005-09-08

申请号：US10790786

申请日：2004-03-03

申请人： Jingyu Lian ,  David Kotecki ,  Hua Shen ,  Robert Laibowitz ,  Katherine Saenger ,  Chenting Lin ,  Nicolas Nagel ,  Yunyu Wang ,  Satish Athavale ,  Thomas Shaw

发明人： Jingyu Lian ,  David Kotecki ,  Hua Shen ,  Robert Laibowitz ,  Katherine Saenger ,  Chenting Lin ,  Nicolas Nagel ,  Yunyu Wang ,  Satish Athavale ,  Thomas Shaw

IPC分类号： H01L21/8242

CPC分类号： H01L28/40 ,  H01L27/10852

摘要： A method for forming high capacitance crystalline dielectric layers with (111) texture is disclosed. In an exemplary embodiment, deposition of a plurality of nuclei is performed at a temperature in the range of about 430 to 460 degrees Celsius, followed by growth of a continuous BSTO dielectric layer at a temperature greater than 600 degrees Celsius. In an exemplary embodiment, a process is disclosed for growing a barium strontium titanium oxide film with high capacitance and thickness of about 30 nm or less.

摘要翻译： 公开了一种形成具有（111）结构的高电容结晶介电层的方法。 在一个示例性实施例中，多个核的沉积在约430至460摄氏度范围内的温度下进行，随后在大于600摄氏度的温度下生长连续的BSTO介电层。 在示例性实施例中，公开了用于生长具有约30nm或更小的高电容和厚度的钡锶氧化钛膜的方法。