公开(公告)号：US10600458B2

公开(公告)日：2020-03-24

申请号：US16105368

申请日：2018-08-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ju-Ho Jeon ,  Han-Gi Jung ,  Hun-Dae Choi

IPC: G11C7/00 ,  G11C7/22 ,  H03L7/081 ,  H03L7/08 ,  G11C29/50 ,  H03K21/02 ,  G11C29/02

Abstract: A memory device and method of operation for latency control in which a source clock signal having a first frequency is divided to provide a divided clock signal having a second frequency that is less than the first frequency as an input to a delay-locked loop circuit in an initialization mode. A locking operation may be performed to align the divided clock signal and a feedback clock signal that is generated by delaying the divided clock signal through the delay-locked loop circuit. A loop delay of the delay-locked loop circuit is measured after the locking operation is completed. The latency control is performed efficiently by measuring the loop delay using the divided clock signal in the initialization mode.

公开(公告)号：US11888489B2

公开(公告)日：2024-01-30

申请号：US17888199

申请日：2022-08-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junsub Yoon ,  Hun-Dae Choi

IPC: H03L7/081 ,  G11C7/22 ,  H03L7/083

CPC classification number: H03L7/0818 ,  G11C7/222 ,  G11C7/225 ,  H03L7/083 ,  H03L7/0814 ,  H03L7/0816

Abstract: In some embodiments of the present disclosure, a delay locked loop includes a coarse delay circuit configured to delay a reference clock signal to generate a first clock signal, a fine delay circuit configured to delay the first clock signal to generate a second clock signal, a first delay circuit configured to delay the second clock signal to generate a third clock signal, a second delay circuit configured to delay the first clock signal to generate a fourth clock signal, a third delay circuit configured to delay the fourth clock signal to generate a fifth clock signal, a phase detector configured to detect a phase difference between the reference clock signal and the fifth clock signal, and a controller configured to adjust, a first delay amount of the coarse delay circuit, a second delay amount of the fine delay circuit and a third delay amount of the third delay circuit.

公开(公告)号：US10367490B2

公开(公告)日：2019-07-30

申请号：US16026145

申请日：2018-07-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wangsoo Kim ,  Hangi Jung ,  Kiduk Park ,  Yoo-Chang Sung ,  Jae-Hun Jung ,  Cheongryong Cho ,  Hun-Dae Choi

IPC: H03K5/13 ,  H04B1/04 ,  H03K5/00

Abstract: An electronic circuit may include a driver, a delay circuit, a strength control circuit, and an adder circuit. The driver may generate a second signal based on a first signal. The delay circuit may delay the first signal by as much as a reference time, to generate a third signal. The strength control circuit may adjust an amplitude of the third signal to generate a fourth signal. The adder circuit may add the second signal and the fourth signal to generate a fifth signal. In a first time interval determined based on the reference time, an amplitude of the fifth signal may be greater than an amplitude of the second signal. In a second time interval except for the first time interval, the amplitude of the fifth signal may be smaller than the amplitude of the second signal. In the second time interval, the amplitude of the fifth signal may be smaller than an amplitude of the first signal.

公开(公告)号：US10320398B2

公开(公告)日：2019-06-11

申请号：US15697885

申请日：2017-09-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Juho Jeon ,  Hun-Dae Choi

IPC: H03L7/081 ,  G11C7/10 ,  G11C7/22 ,  H03L7/10 ,  G11C29/02 ,  H03L7/087 ,  H03L7/197 ,  H03L7/22

Abstract: A delay locked loop according to some example embodiments of the inventive concepts may include first, second, and third delay circuits, first and second phase detectors, and first and second controllers. The first delay circuit may generate a first clock by delaying a reference clock. The second and third delay circuits may be configured to generate a second and third clock respectively by delaying the first clock. The first and second phase detector may be configured to detect a phase difference between the second clock and the third clock and the third clock respectively. The first controller may be configured to adjust a delay of the third delay circuit using a detection result of the first phase detector. The second controller may be configured to adjust a delay of the first delay circuit using a detection result of the second phase detector.

公开(公告)号：US09590628B2

公开(公告)日：2017-03-07

申请号：US14976716

申请日：2015-12-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： SukYong Kang ,  Hun-Dae Choi

IPC: G11C7/22 ,  G11C7/10 ,  G11C7/06 ,  G11C11/4076 ,  G11C11/406 ,  H03K19/0175 ,  G11C5/14 ,  G11C7/14 ,  G11C29/02 ,  G11C7/12

CPC classification number: H03K19/017509 ,  G11C5/147 ,  G11C7/062 ,  G11C7/1084 ,  G11C7/12 ,  G11C7/14 ,  G11C7/22 ,  G11C7/222 ,  G11C29/028 ,  G11C2207/2254

Abstract: Provided are a reference voltage training device and a method thereof. The reference voltage training device includes a comparator configured to compare a toggle signal with a reference voltage and output a comparison signal, a duty cycle detector configured to check a duty ratio of the comparison signal, and a reference voltage level changing unit configured to fix the reference voltage when the duty ratio meets a predetermined condition and to change a level of the reference voltage when the duty ratio does not meet the predetermined condition. The comparator outputs a changed comparison signal using the changed reference voltage.

Abstract translation: 提供了一种参考电压训练装置及其方法。 参考电压训练装置包括：比较器，被配置为将触发信号与参考电压进行比较并输出比较信号;配置为检查比较信号的占空比的占空比检测器;以及参考电压电平改变单元， 当占空比满足预定条件时的参考电压，并且当占空比不满足预定条件时改变参考电压的电平。 比较器使用改变的参考电压输出改变的比较信号。

公开(公告)号：US11651813B2

公开(公告)日：2023-05-16

申请号：US17380206

申请日：2021-07-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hun-Dae Choi ,  Ga Ram Choi

IPC: G11C11/4076 ,  H03K5/156 ,  H03K7/08 ,  H03L7/085 ,  H03L7/06 ,  G11C7/22 ,  G11C11/4093 ,  G11C11/4091 ,  G11C11/4096

CPC classification number: G11C11/4076 ,  G11C7/22 ,  G11C11/4091 ,  G11C11/4093 ,  G11C11/4096

Abstract: A clock correction circuit in which a correction accuracy of a duty cycle is increased is provided. The clock correction circuit comprises a delay-locked loop circuit configured to receive a first clock signal and generate a second clock signal obtained by delaying the first clock signal; a first duty cycle correction circuit configured to receive the second clock signal and generate a first correction clock signal obtained by correcting a duty cycle of the second clock signal; and a duty cycle detection circuit which includes a second duty cycle correction circuit and an error code generation circuit, wherein the error code generation circuit receives the first correction clock signal, and generates a first error code as to whether to correct the duty cycle of the second clock signal on the basis of the first correction clock signal, the second duty cycle correction circuit generates a second correction clock signal obtained by correcting the duty cycle of the first correction clock signal in response to the first error code, the error code generation circuit generates a second error code as to whether to correct the duty cycle of the second clock signal on the basis of the second correction clock signal, and the first duty cycle correction circuit receives the second error code, and generates a third correction clock signal obtained by correcting the duty cycle of the second clock signal in response to the second error code.

公开(公告)号：US11342011B2

公开(公告)日：2022-05-24

申请号：US17012723

申请日：2020-09-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hun-Dae Choi ,  Hwapyong Kim

IPC: G11C7/22 ,  G11C8/06 ,  G11C7/06 ,  G11C8/10 ,  G11C7/10

Abstract: Inventive concepts relates to a semiconductor memory device. The semiconductor memory device may include a first buffer configured to receive a first signal, a second buffer configured to receive a second signal, a detector configured to compare a first phase of the first signal received by the first buffer to a second phase of the second signal received by the second buffer and to generate a detection signal, and a corrector activated or inactivated in response to a detection signal. The corrector may be configured to correct the first signal received by the first buffer and the second signal received by the second buffer, when the corrector is activated in response to the detection signal.

公开(公告)号：US10923181B2

公开(公告)日：2021-02-16

申请号：US16248004

申请日：2019-01-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ju Ho Jeon ,  Hun-Dae Choi

IPC: G11C11/4093 ,  G11C11/4094 ,  H03K19/00 ,  G11C11/4076 ,  G11C11/4096 ,  G11C11/408

Abstract: The semiconductor memory device including a data strobe signal input buffer configured to receive a data strobe signal and generate an input data strobe signal, a data input buffer configured to receive data delayed by a first delay time compared to the data strobe signal and generate input data, a latency control signal generator configured to generate and activate a first on-die termination control signal during a first period in which the data strobe signal is applied in response to receiving a write command, a first on-die termination control circuit configured to vary a first variable resistance code in response to the first on-die termination control signal, and a data strobe signal termination circuit configured to terminate the data strobe signal and including a first on-die termination resistor, a resistance value of which varies in response to the first variable resistance code may be provided.

公开(公告)号：US10748585B2

公开(公告)日：2020-08-18

申请号：US16353429

申请日：2019-03-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hun-Dae Choi

IPC: G11C7/10 ,  G11C11/408 ,  H03K17/687

Abstract: A calibration circuit includes first and second pull-up units each receiving a pull-up code and connected between a pad connected with an external resistor and a first power supply voltage, a pull-down unit connected between the pad and a second power supply voltage and receiving a pull-down code, a comparator comparing a first voltage with a reference voltage and then compare a second voltage with the reference voltage, a first digital filter adjusting the pull-up code based on a first comparison result of the first voltage with the reference voltage, and a second digital filter adjusting the pull-down code based on a second comparison result of the second voltage with the reference voltage.

公开(公告)号：US20200027489A1

公开(公告)日：2020-01-23

申请号：US16357671

申请日：2019-03-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hun-Dae Choi ,  Hwapyong Kim

IPC: G11C7/22 ,  G11C8/06 ,  G11C7/10 ,  G11C8/10 ,  G11C7/06

Abstract: Inventive concepts relates to a semiconductor memory device. The semiconductor memory device may include a first buffer configured to receive a first signal, a second buffer configured to receive a second signal, a detector configured to compare a first phase of the first signal received by the first buffer to a second phase of the second signal received by the second buffer and to generate a detection signal, and a corrector activated or inactivated in response to a detection signal. The corrector may be configured to correct the first signal received by the first buffer and the second signal received by the second buffer, when the corrector is activated in response to the detection signal.