Abstract:
A test method of the semiconductor memory device including a memory cell array and an anti-fuse array includes detecting failed cells included in the memory cell array; determining a fail address corresponding to the detected failed cells; storing the determined fail address in a first region of the memory cell array; and reading the fail address stored in the first region to program the read fail address in the anti-fuse array. According to the test method of a semiconductor memory device and the semiconductor memory system, since the test operation can be performed without an additional memory for storing an address, the semiconductor memory device and the test circuit can be embodied by a small area.
Abstract:
A method of modeling damages to a crystal caused by an incident particle includes obtaining particle information and crystal information; estimating energy loss of the incident particle based on the particle information and the crystal information; estimating a volume of a vacancy based on the energy loss; estimating a vacancy reaction based on the crystal information and the volume of the vacancy; and generating output data based on the vacancy reaction, the output data including quantification data of the damages.
Abstract:
An error correcting method of a semiconductor memory device includes receiving first data from outside the semiconductor memory device. First check bits are generated based on the first data and a first parity generator matrix. The first parity generator matrix includes a plurality of columns of bits. The plurality of columns of bits are arranged in a plurality of parity generator matrix groups. An error correcting code (ECC) code word including a plurality of ECC code word groups is stored in the plurality of memory cell groups. Each of the plurality of ECC code word groups have the first data and the first check bits. The plurality of ECC code word groups correspond to the plurality of parity generator matrix groups, respectively. For each parity generator matrix group of the first parity generator matrix, a result value of a bit-by-bit exclusive OR (XOR) operation performed on any two columns included in the parity generator matrix group is equal to a column number of a column that is not included in the parity generator matrix group. Thus, when a first ECC code word group, from among the plurality of ECC code word groups, includes error bits, a miscorrected bit that would be caused by the error bits as a result of performing an error correction operation on the first ECC code word group is located in an ECC code word group other than the first ECC code word group.
Abstract:
A method for controlling a voltage based on a temperature and a terminal supporting the same are provided. The terminal includes a temperature sensor for detecting a temperature of at least one location of the inside and of the outside of at least one system and a voltage control unit for adjusting the voltage supplied to the at least one system according to the temperature detected by the temperature sensor.
Abstract:
Various embodiments of the present disclosure may provide an electronic device that includes: a first plate directed in a first direction, a second plate directed in a second direction opposite to the first direction, and a side member configured to surround at least a part of the space between the first and second plates; a first printed circuit board (PCB) that is disposed between the first and second plates and includes at least one processor; a second printed circuit board (PCB) that is disposed between the first printed circuit board and the second plate and includes at least one antenna pattern; and a temperature sensor disposed to measure the temperature of at least a part of the second printed circuit board. Other various embodiments are possible.
Abstract:
A semiconductor memory cell array is provided which includes a first memory cell array area including first group memory cells arranged in a chip in a matrix of rows and columns and having a first operating speed; and a second memory cell array area including second group memory cells arranged in the chip in a matrix of rows and columns and having a second operating speed different from the first operating speed. The first and second memory cell array areas are accessed by addressing of a DRAM controller.
Abstract:
An antenna device and an electronic device including the same are provided. The antenna device includes a housing that includes a first plate, a second plate facing a direction opposite to the first plate, and a side member surrounding a space between the first plate and the second plate, a display viewable through at least a portion of the first plate, an antenna assembly disposed within the housing wherein the antenna assembly includes a first printed circuit board, a second printed circuit board, at least one structure interconnecting the first printed circuit board and the second printed circuit board and including conductive paths, a plurality of conductive patterns, and a wireless communication circuit, a flexible printed circuit board, and a third printed circuit board.
Abstract:
An electronic device may be provided and include: a printed circuit board includes a first side and a second side perpendicular to the first side; a plurality of solder balls on a surface of the printed circuit board and spaced apart from the first side and the second side; an electronic component including at least one circuit, the electronic component on at least some of the plurality of solder balls; a resin along the first side and filling a portion of a space between the surface of the printed circuit board and the electronic component; and a blocking structure in or on the surface of the printed circuit board, the blocking structure being between the plurality of solder balls and the first side, and extending along the first side such as to separate the at least some of the plurality of solder balls from the resin.
Abstract:
A system is described for protecting the edge region of a substrate during a plasma process. The system includes an outer ring with a plurality of outer uneven portions and an inner ring also with a plurality of inner uneven portions. The outer ring covers the edge region of the substrate. The inner ring may rotate around the center point of the outer ring. When the inner ring is rotated, each of the inner uneven portions and each the outer uneven portions may slide by each other to overlap and to form openings. Changes of the opening ratios in the gaps (or the overlap ratios of the inner and outer uneven portions) may change a thickness of a plasma sheath. Thus, the plasma sheath in an edge region of the substrate may be readily controlled.
Abstract:
In an embodiment according to the present disclosure, disclosed is an electronic device including a display, a first housing, a second housing at least partially overlapping and being movable with respect to the first housing, a first conductive region formed or disposed inside the first housing, and a second conductive region formed or disposed inside the second housing so as to at least partially overlap with the first conductive region when the first housing is moved with respect to the first housing, a display in which at least the first region is exposed to the outside of an electronic device through a front surface of the electronic device, and at least one processor in which, when the electronic device is switched from the first state to the second state, a second region extending from the first region of the display is withdrawn from the inside of the first housing and exposed to the outside of the electronic device along with the first region and, when the electronic device is switched from the second state to the first state, is introduced into the inside of the first housing and operatively connected to the display. The at least one processor identifies a capacitance value, based on an overlapped region of the first conductive region and the second conductive region, and determines an externally exposed region of the display, based on the identified capacitance value, and controls the region determined to be exposed outside, to an activated state, and controls the remaining region except the region determined to be exposed outside, to an inactivated state. In addition to this, various embodiments identified through the specification are possible.