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    Barrier modulated cell structures with intrinsic vertical bit line architecture
    11.
    发明授权
    Barrier modulated cell structures with intrinsic vertical bit line architecture 有权

    公开(公告)号：US10388870B2

    公开(公告)日：2019-08-20

    申请号：US15793247

    申请日：2017-10-25

    Applicant: SANDISK TECHNOLOGIES LLC

    Inventor： Perumal Ratnam ,  Tanmay Kumar ,  Christopher Petti

    IPC: G11C13/00 ,  H01L27/24 ,  H01L45/00

    Abstract: Systems and methods for reducing leakage currents through unselected memory cells of a memory array including setting an adjustable resistance bit line structure connected to the unselected memory cells into a high resistance state or a non-conducting state during a memory operation are described. The adjustable resistance bit line structure may comprise a bit line structure in which the resistance of an intrinsic (or near intrinsic) polysilicon portion of the bit line structure may be adjusted via an application of a voltage to a select gate portion of the bit line structure that is electrically isolated from the intrinsic polysilicon portion (e.g., via an oxide layer between the intrinsic polysilicon portion and the select gate portion). The memory cells may comprise a first conductive metal oxide (e.g., titanium oxide) that abuts a second conductive metal oxide (e.g., aluminum oxide) that abuts a layer of amorphous silicon.

    Data rewrite during refresh window
    17.
    发明授权
    Data rewrite during refresh window 有权

    公开(公告)号：US10885991B2

    公开(公告)日：2021-01-05

    申请号：US16359846

    申请日：2019-03-20

    Applicant: SanDisk Technologies LLC

    Inventor： Ward Parkinson ,  Martin Hassner ,  Nathan Franklin ,  Christopher Petti

    IPC: G11C16/34 ,  G06F3/06 ,  G06F11/08 ,  G06F12/02

    Abstract: Apparatuses, systems, methods, and computer program products are disclosed for data rewrite operations. A non-volatile memory device comprises a non-volatile memory medium. A non-volatile memory device is configured to determine an error metric for a non-volatile memory medium in response to a read request for the non-volatile memory medium. A non-volatile memory device is configured to receive a refresh command from a controller over a bus. A non-volatile memory device is configured to rewrite data from a non-volatile memory medium during a predefined time period after receiving a refresh command in response to an error metric satisfying an error threshold.

    Wordline sidewall recess for integrating planar selector device
    20.
    发明授权
    Wordline sidewall recess for integrating planar selector device 有权

    公开(公告)号：US10109679B2

    公开(公告)日：2018-10-23

    申请号：US15432544

    申请日：2017-02-14

    Applicant: SANDISK TECHNOLOGIES LLC

    Inventor： Yangyin Chen ,  Christopher Petti

    IPC: H01L47/00 ,  H01L27/24 ,  G11C13/00 ,  H01L23/528 ,  H01L23/532 ,  H01L45/00 ,  H01L27/12 ,  H01L29/786

    Abstract: Systems and methods for fabricating a non-volatile memory with integrated selector devices (or steering devices) are described. Each memory cell within a memory array may be placed in series with a selector device, such as a diode or other non-linear current-voltage device, in order to reduce leakage currents through unselected memory cells during a memory operation. In some cases, fabricating a selector device within a memory hole region may be difficult due to the dimensions of the selector device. A wordline sidewall recess process or a wordline sidewall recess with a replacement metal gate process may be used to integrate selector devices with memory cells outside of the memory hole region. By fabricating non-linear selector devices outside of the memory hole region, the area of the memory array may be reduced.

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