公开(公告)号：US20240395825A1

公开(公告)日：2024-11-28

申请号：US18789755

申请日：2024-07-31

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Wataru UESUGI ,  Hikaru TAMURA ,  Atsuo ISOBE

IPC: H01L27/12 ,  G11C7/04 ,  H01L29/04 ,  H01L29/78 ,  H01L29/786 ,  H03K19/00 ,  H03K19/0185

Abstract: A retention circuit provided in a logic circuit enables power gating. The retention circuit includes a first terminal, a node, a capacitor, and first to third transistors. The first transistor controls electrical connection between the first terminal and an input terminal of the logic circuit. The second transistor controls electrical connection between an output terminal of the logic circuit and the node. The third transistor controls electrical connection between the node and the input terminal of the logic circuit. A gate of the first transistor is electrically connected to a gate of the second transistor. In a data retention period, the node becomes electrically floating. The voltage of the node is held by the capacitor.

公开(公告)号：US20170330873A1

公开(公告)日：2017-11-16

申请号：US15667672

申请日：2017-08-03

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hikaru TAMURA ,  Naoaki TSUTSUI ,  Atsuo ISOBE

IPC: H01L27/02 ,  H01L29/786 ,  H01L27/12 ,  H01L27/06 ,  H01L23/528 ,  H01L23/532 ,  H03K19/00

CPC classification number: H01L27/0207 ,  H01L23/528 ,  H01L23/53214 ,  H01L23/53228 ,  H01L23/53257 ,  H01L27/0688 ,  H01L27/1207 ,  H01L27/1274 ,  H01L29/7869 ,  H03K19/0008

Abstract: To provide a semiconductor device including element layers that are stacked. A first wiring layer and a second wiring layer are stacked between a first element layer and a second element layer. A third wiring layer and a fourth wiring layer are stacked over the second element layer. Transistors of logic cells are provided in the first element layer. Wirings of the logic cells are provided in the first wiring layer or the second wiring layer. Input ports and output ports of the logic cells are provided in the third wiring layer. The input port of one of the logic cells is connected to the output port of another logic cell through the wiring of the third wiring layer or the fourth wiring layer. Connecting the logic cells through the wiring layers over the second element layer improves the efficiency of steps of arranging and connecting the logic cells.

公开(公告)号：US20160380631A1

公开(公告)日：2016-12-29

申请号：US15262186

申请日：2016-09-12

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hikaru TAMURA

IPC: H03K19/00

CPC classification number: H03K19/0013 ,  G09G3/20 ,  G11C7/1006 ,  G11C7/12 ,  G11C11/00 ,  G11C11/401 ,  G11C11/4094 ,  H01L27/10814 ,  H03K19/0966

Abstract: A drive capability of a dynamic logic circuit is improved. A logic circuit includes a dynamic logic circuit, a first output node, a first transistor that is diode-connected, and a capacitor. The dynamic logic circuit includes a second output node. The first transistor and transistors in the dynamic logic circuit have an n-type conductivity or a p-type conductivity. The first output node is electrically connected to a first terminal of the capacitor, and the second output node is electrically connected to a second terminal of the capacitor. A first terminal of the first transistor is electrically connected to the first output node, and a first voltage is input to a second terminal of the first transistor.

公开(公告)号：US20160293649A1

公开(公告)日：2016-10-06

申请号：US15177460

申请日：2016-06-09

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yoshiyuki KUROKAWA ,  Takayuki IKEDA ,  Hikaru TAMURA ,  Munehiro KOZUMA ,  Masataka IKEDA ,  Takeshi AOKI

IPC: H01L27/146 ,  H04N5/361 ,  H04N5/374 ,  H04N5/378 ,  H01L29/786 ,  H01L31/105

CPC classification number: H01L27/14616 ,  H01L27/14603 ,  H01L27/14632 ,  H01L27/14636 ,  H01L27/14643 ,  H01L29/7869 ,  H01L31/1055 ,  H04N5/361 ,  H04N5/374 ,  H04N5/378

Abstract: In a CMOS image sensor in which a plurality of pixels is arranged in a matrix, a transistor in which a channel formation region includes an oxide semiconductor is used for each of a charge accumulation control transistor and a reset transistor which are in a pixel portion. After a reset operation of the signal charge accumulation portion is performed in all the pixels arranged in the matrix, a charge accumulation operation by the photodiode is performed in all the pixels, and a read operation of a signal from the pixel is performed per row. Accordingly, an image can be taken without a distortion.

公开(公告)号：US20150370313A1

公开(公告)日：2015-12-24

申请号：US14741910

申请日：2015-06-17

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hikaru TAMURA

IPC: G06F1/32 ,  H01L27/12 ,  H01L29/786 ,  G06F11/14

CPC classification number: G06F1/3296 ,  G06F1/3237 ,  G06F1/3243 ,  G06F1/3287 ,  G06F11/1456 ,  G11C5/14 ,  G11C11/401 ,  G11C11/4074 ,  G11C14/0054 ,  H01L27/1255 ,  H01L29/7869 ,  Y02D10/128 ,  Y02D10/152 ,  Y02D10/171 ,  Y02D10/172

Abstract: Power consumption is reduced. A semiconductor device includes an arithmetic processing circuit, a power supply circuit, a power management unit (PMU), and a power switch. The arithmetic processing circuit includes a storage circuit for retaining generated data. The storage circuit includes a backup circuit including a transistor and a capacitor. When a control signal for transition to a resting state is input from the arithmetic processing circuit to the PMU, the PMU performs voltage scaling operation for lowering the power supply potential of the arithmetic processing circuit. When the time of the voltage scaling operation is longer than the time of the resting state, the PMU performs power gating operation for stopping supply of power to the arithmetic processing circuit. The storage circuit performs data backup operation before the PMU performs the voltage scaling operation.

Abstract translation: 功耗降低。 半导体器件包括运算处理电路，电源电路，电源管理单元（PMU）和电源开关。 算术处理电路包括用于保留生成数据的存储电路。 存储电路包括具有晶体管和电容器的备用电路。 当从运算处理电路向PMU输入转移到静止状态的控制信号时，PMU进行用于降低运算处理电路的电源电位的电压缩放运算。 当电压缩放操作的时间长于静止状态的时间时，PMU进行用于停止向运算处理电路供电的电力门控操作。 存储电路在PMU执行电压缩放操作之前执行数据备份操作。

公开(公告)号：US20150340094A1

公开(公告)日：2015-11-26

申请号：US14712207

申请日：2015-05-14

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hikaru TAMURA

IPC: G11C16/10

CPC classification number: G11C16/10 ,  G11C7/1078 ,  G11C7/16 ,  G11C11/40

Abstract: Provided is a semiconductor device capable of reducing its area, operating at a high speed, or reducing its power consumption. A circuit 50 is used as a memory circuit with a function of performing an arithmetic operation. One of a circuit 80 and a circuit 90 has a region overlapping with at least part of the other of the circuit 80 and the circuit 90. Accordingly, the circuit 50 can perform the arithmetic operation that is essentially performed in the circuit 60; thus, a burden of the arithmetic operation on the circuit 60 can be reduced. Moreover, the number of times of data transmission and reception between the circuits 50 and 60 can be reduced. Furthermore, the circuit 50 functioning as a memory circuit can have a function of performing an arithmetic operation while the increase in the area of the circuit 50 is suppressed.

Abstract translation: 提供能够减小面积，高速运转或降低功耗的半导体装置。 电路50用作具有执行算术运算功能的存储电路。 电路80和电路90之一具有与电路80和电路90中的另一个的至少一部分重叠的区域。因此，电路50可以执行基本上在电路60中执行的算术运算; 因此，可以减少对电路60的算术运算的负担。 此外，可以减少电路50和60之间的数据发送和接收的次数。 此外，用作存储器电路的电路50可以具有在抑制电路50的面积的增加的同时执行算术运算的功能。

公开(公告)号：US20140240294A1

公开(公告)日：2014-08-28

申请号：US14272735

申请日：2014-05-08

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yoshiyuki KUROKAWA ,  Takayuki IKEDA ,  Hikaru TAMURA ,  Munehiro KOZUMA ,  Masataka IKEDA

IPC: G06F3/042 ,  H01L27/144 ,  H01L27/146 ,  H01L31/0232

CPC classification number: G06F3/0421 ,  G06F3/0428 ,  H01L27/144 ,  H01L27/14625 ,  H01L31/0232 ,  H01L31/02327

Abstract: Influence of external light is suppressed. With a photodetector including a photodetector circuit which generates a data signal in accordance with illuminance of incident light and a light unit which overlaps with the photodetector circuit, a first data signal is generated by the photodetector circuit when the light unit is in an ON state, a second data signal is formed by the photodetector circuit when the light unit is in an OFF state, and the first data signal and the second data signal are compared, so that a difference data signal that is data of a difference between the two compared data signals is generated.

Abstract translation: 外部光的影响被抑制。 利用包括根据入射光的照度产生数据信号的光电检测器电路和与光电检测器电路重叠的光单元的光检测器，当光单元处于导通状态时，由光检测器电路产生第一数据信号， 当光单元处于关闭状态时，第二数据信号由光检测器电路形成，并且比较第一数据信号和第二数据信号，使得作为两个比较数据之间的差的数据的差分数据信号 生成信号。

公开(公告)号：US20220328530A1

公开(公告)日：2022-10-13

申请号：US17845112

申请日：2022-06-21

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Wataru UESUGI ,  Hikaru TAMURA ,  Atsuo ISOBE

IPC: H01L27/12 ,  H01L29/786 ,  H01L49/02 ,  H01L29/04 ,  H01L29/78 ,  H03K19/00 ,  H03K19/0185 ,  G11C7/04

Abstract: A retention circuit provided in a logic circuit enables power gating. The retention circuit includes a first terminal, a node, a capacitor, and first to third transistors. The first transistor controls electrical connection between the first terminal and an input terminal of the logic circuit. The second transistor controls electrical connection between an output terminal of the logic circuit and the node. The third transistor controls electrical connection between the node and the input terminal of the logic circuit. A gate of the first transistor is electrically connected to a gate of the second transistor. In a data retention period, the node becomes electrically floating. The voltage of the node is held by the capacitor.

公开(公告)号：US20170373092A1

公开(公告)日：2017-12-28

申请号：US15644916

申请日：2017-07-10

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Wataru UESUGI ,  Hikaru TAMURA ,  Atsuo ISOBE

IPC: H01L27/12 ,  H03K19/00 ,  H01L49/02 ,  H01L29/78 ,  G11C7/04 ,  H01L29/04 ,  H03K19/0185 ,  H01L29/786

CPC classification number: H01L27/1207 ,  G11C7/04 ,  H01L27/1225 ,  H01L27/1255 ,  H01L28/40 ,  H01L29/04 ,  H01L29/045 ,  H01L29/7849 ,  H01L29/78648 ,  H01L29/78696 ,  H03K19/0008 ,  H03K19/018514

Abstract: A retention circuit provided in a logic circuit enables power gating. The retention circuit includes a first terminal, a node, a capacitor, and first to third transistors. The first transistor controls electrical connection between the first terminal and an input terminal of the logic circuit. The second transistor controls electrical connection between an output terminal of the logic circuit and the node. The third transistor controls electrical connection between the node and the input terminal of the logic circuit. A gate of the first transistor is electrically connected to a gate of the second transistor. In a data retention period, the node becomes electrically floating. The voltage of the node is held by the capacitor.

公开(公告)号：US20170077763A1

公开(公告)日：2017-03-16

申请号：US15362175

申请日：2016-11-28

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Takeshi OSADA ,  Hikaru TAMURA

IPC: H02J50/20 ,  H04B5/00 ,  G06K19/077 ,  H02J7/02 ,  H02J50/80

CPC classification number: H02J50/12 ,  B60L1/00 ,  B60L11/1811 ,  B60L11/182 ,  G06K19/0701 ,  G06K19/0705 ,  G06K19/0723 ,  G06K19/0724 ,  G06K19/07767 ,  G06K19/07773 ,  G06K19/07779 ,  G06K19/07783 ,  H01L27/1255 ,  H01L27/1266 ,  H01L2223/6677 ,  H02J50/20 ,  H02J50/80 ,  H04B5/0037 ,  Y02D70/00 ,  Y02D70/166 ,  Y02D70/26 ,  Y02T90/16

Abstract: An object is to provide a semiconductor device that is capable of wireless communication, such as an RFID tag, which can transmit and receive individual information without checking remaining capacity of a battery or changing batteries due to deterioration with time in the battery for a drive power supply voltage, and maintain a favorable a transmission/reception state even when electric power of an electromagnetic wave from a reader/writer is not sufficient. The semiconductor device includes a signal processing circuit, a first antenna circuit connected to the signal processing circuit, an antenna circuit group, a rectifier circuit-group and a battery connected to the signal processing circuit. The first antenna circuit transmits and receives a signal for transmitting data stored in the signal processing circuit and drives a power supply circuit, and each antenna circuit of the antenna circuit group receives a signal for charging the battery and includes an antenna which has a different corresponding frequency.

Abstract translation: 本发明的目的是提供能够进行无线通信的半导体装置，例如RFID标签，其能够在不检查电池的剩余容量的情况下发送和接收个别信息，或者由于电池中的驱动电力随时间的变化而改变电池 电源电压，并且即使来自读取器/写入器的电磁波的电力不足，也保持良好的发送/接收状态。 半导体器件包括信号处理电路，连接到信号处理电路的第一天线电路，天线电路组，整流器电路组和连接到信号处理电路的电池。 第一天线电路发送和接收用于发送存储在信号处理电路中的数据的信号并驱动电源电路，天线电路组的每个天线电路接收用于对电池充电的信号，并且包括具有不同对应的天线 频率。