公开(公告)号：US09812466B2

公开(公告)日：2017-11-07

申请号：US14817709

申请日：2015-08-04

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Tomoaki Atsumi ,  Masayuki Sakakura ,  Yoshitaka Yamamoto ,  Jun Koyama ,  Tetsuhiro Tanaka ,  Kazuki Tanemura

IPC: H01L27/12 ,  H01L29/786

CPC classification number: H01L27/1225 ,  H01L29/78648

Abstract: A highly reliable semiconductor device that is suitable for high-speed operation is provided. A semiconductor device includes a first circuit, a second circuit, and a third circuit. The first circuit has an arithmetic processing function. The second circuit includes a memory circuit. The memory circuit includes a transistor which includes a first conductor, a second conductor, a first insulator, a second insulator, and a semiconductor. The first conductor includes a region overlapping the semiconductor with the first insulator positioned between the first conductor and the semiconductor. The second conductor includes a region overlapping the semiconductor with the second insulator positioned between the second conductor and the semiconductor. The first conductor is capable of selecting on or off of the transistor. The third circuit is electrically connected to the second conductor, and is capable of changing the potential of the second conductor in synchronization with an operation of the transistor.

公开(公告)号：US09672873B2

公开(公告)日：2017-06-06

申请号：US15159919

申请日：2016-05-20

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yoshitaka Yamamoto ,  Kiyoshi Kato

IPC: G11C11/00 ,  G11C11/14 ,  G11C5/14 ,  H01L27/108 ,  H01L27/06 ,  H01L29/786 ,  G11C8/16 ,  G11C11/405 ,  G11C11/408 ,  G11C11/56 ,  H01L27/12 ,  G11C7/12 ,  G11C8/08 ,  G11C8/10 ,  G11C11/24 ,  G11C11/409 ,  H01L23/528 ,  H01L27/105 ,  H01L29/24 ,  H01L27/1156

CPC classification number: G11C5/14 ,  G11C7/12 ,  G11C8/08 ,  G11C8/10 ,  G11C8/16 ,  G11C11/24 ,  G11C11/405 ,  G11C11/4087 ,  G11C11/409 ,  G11C11/565 ,  G11C2207/108 ,  H01L23/528 ,  H01L27/0688 ,  H01L27/1052 ,  H01L27/10814 ,  H01L27/1082 ,  H01L27/10826 ,  H01L27/10855 ,  H01L27/10858 ,  H01L27/10873 ,  H01L27/10879 ,  H01L27/10897 ,  H01L27/1156 ,  H01L27/1207 ,  H01L27/1225 ,  H01L27/1255 ,  H01L27/1259 ,  H01L29/24 ,  H01L29/786 ,  H01L29/7869

Abstract: A novel semiconductor device where multilevel data can be written and read. The semiconductor device includes first to fifth transistors, a capacitor, a bit line, and a power supply line. Write operation is performed in such a manner that first data is supplied to a gate of the fifth transistor through the first transistor; the first transistor is turned off; second data is supplied to a second electrode of the capacitor through the second transistor to convert the first data into third data; and the second electrode of the capacitor are made electrically floating. The second electrode of the capacitor is initialized to GND through the third transistor. Read operation is performed by charging or discharging the bit line through the fourth transistor and the fifth transistor. The first to third transistors are preferably oxide semiconductor transistors.

公开(公告)号：US09269822B2

公开(公告)日：2016-02-23

申请号：US14479623

申请日：2014-09-08

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yoshitaka Yamamoto ,  Tetsuhiro Tanaka ,  Takayuki Inoue ,  Hideomi Suzawa ,  Yasuhiko Takemura

IPC: H01L29/78 ,  H01L29/786 ,  H01L29/66 ,  G11C16/00 ,  H01L29/788 ,  H01L29/49

CPC classification number: H01L29/7869 ,  G11C11/24 ,  G11C16/00 ,  G11C16/0466 ,  H01L29/4908 ,  H01L29/66969 ,  H01L29/78606 ,  H01L29/78648 ,  H01L29/78696 ,  H01L29/7881

Abstract: A method for manufacturing a semiconductor device with adjusted threshold is provided. In a semiconductor device including a semiconductor, a source or drain electrode electrically connected to the semiconductor, a first gate electrode and a second gate electrode between which the semiconductor is provided, a charge trap layer provided between the first gate electrode and the semiconductor, and a gate insulating layer provided between the second gate electrode and the semiconductor, a threshold is increased by trapping electrons in the charge trap layer by keeping a potential of the first gate electrode at a potential higher than a potential of the source or drain electrode for 1 second or more while heating. After the threshold adjustment process, the first gate electrode is removed or insulated from other circuits. Alternatively, a resistor may be provided between the first gate electrode and other circuits.

Abstract translation: 提供一种用于制造具有调节阈值的半导体器件的方法。 在包括半导体，与半导体电连接的源电极或漏电极的半导体器件中，设置有半导体的第一栅电极和第二栅电极，设置在第一栅电极和半导体之间的电荷陷阱层，以及 设置在第二栅电极和半导体之间的栅极绝缘层，通过将第一栅电极的电位保持在高于源电极或漏电极的电位的电位为1，通过在电荷陷阱层中俘获电子来增加阈值 第二次或多次加热。 在阈值调整处理之后，第一栅电极被去除或与其它电路绝缘。 或者，可以在第一栅极电极和其它电路之间设置电阻器。

公开(公告)号：US20150179774A1

公开(公告)日：2015-06-25

申请号：US14570422

申请日：2014-12-15

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Naoto Yamade ,  Yoshitaka Yamamoto ,  Hideomi Suzawa ,  Masayuki Sakakura ,  Yuhei Sato ,  Yasumasa Yamane

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/383 ,  H01L21/465 ,  H01L21/441 ,  H01L21/425 ,  H01L29/786 ,  H01L21/477

CPC classification number: H01L29/66969 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/0262 ,  H01L21/02631 ,  H01L21/383 ,  H01L21/425 ,  H01L21/441 ,  H01L21/465 ,  H01L21/477 ,  H01L29/78648 ,  H01L29/7869 ,  H01L29/78696

Abstract: The semiconductor device is manufactured by the following method. A first oxide semiconductor film is formed over a first gate electrode and a first insulating film, oxygen is added to the first oxide semiconductor film, and then a second oxide semiconductor film is formed over the first oxide semiconductor film. Then, heat treatment is performed. Next, part of the first insulating film, part of the first oxide semiconductor film, and part of the second oxide semiconductor film are etched to form a first gate insulating film having a projection. Next, a pair of electrodes is formed over the second oxide semiconductor film, and a third oxide semiconductor film is formed over the second oxide semiconductor film and the pair of electrodes. Then, a second gate insulating film is formed over the third oxide semiconductor film, and a second gate electrode is formed over the second gate insulating film.

Abstract translation: 半导体器件通过以下方法制造。 在第一栅电极和第一绝缘膜上形成第一氧化物半导体膜，在第一氧化物半导体膜上添加氧，然后在第一氧化物半导体膜上形成第二氧化物半导体膜。 然后进行热处理。 接下来，蚀刻第一绝缘膜的一部分，第一氧化物半导体膜的一部分和第二氧化物半导体膜的一部分，以形成具有突起的第一栅极绝缘膜。 接着，在第二氧化物半导体膜上形成一对电极，在第二氧化物半导体膜和一对电极上形成第三氧化物半导体膜。 然后，在第三氧化物半导体膜上形成第二栅极绝缘膜，在第二栅极绝缘膜上形成第二栅电极。

公开(公告)号：US09882059B2

公开(公告)日：2018-01-30

申请号：US14571981

申请日：2014-12-16

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Akihisa Shimomura ,  Yuhei Sato ,  Yasumasa Yamane ,  Yoshitaka Yamamoto ,  Hideomi Suzawa ,  Tetsuhiro Tanaka ,  Yutaka Okazaki ,  Naoki Okuno ,  Takahisa Ishiyama

IPC: H01L29/786 ,  H01L29/417

CPC classification number: H01L29/7869 ,  H01L29/41733 ,  H01L29/78606 ,  H01L29/78696

Abstract: To provide a transistor having a high on-state current. A semiconductor device includes a first insulator containing excess oxygen, a first oxide semiconductor over the first insulator, a second oxide semiconductor over the first oxide semiconductor, a first conductor and a second conductor which are over the second oxide semiconductor and are separated from each other, a third oxide semiconductor in contact with side surfaces of the first oxide semiconductor, a top surface and side surfaces of the second oxide semiconductor, a top surface of the first conductor, and a top surface of the second conductor, a second insulator over the third oxide semiconductor, and a third conductor facing a top surface and side surfaces of the second oxide semiconductor with the second insulator and the third oxide semiconductor therebetween. The first oxide semiconductor has a higher oxygen-transmitting property than the third oxide semiconductor.

公开(公告)号：US09450080B2

公开(公告)日：2016-09-20

申请号：US14570422

申请日：2014-12-15

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Naoto Yamade ,  Yoshitaka Yamamoto ,  Hideomi Suzawa ,  Masayuki Sakakura ,  Yuhei Sato ,  Yasumasa Yamane

IPC: H01L21/00 ,  H01L29/66 ,  H01L29/786 ,  H01L21/02 ,  H01L21/477 ,  H01L21/465 ,  H01L21/441 ,  H01L21/425 ,  H01L21/383

CPC classification number: H01L29/66969 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/0262 ,  H01L21/02631 ,  H01L21/383 ,  H01L21/425 ,  H01L21/441 ,  H01L21/465 ,  H01L21/477 ,  H01L29/78648 ,  H01L29/7869 ,  H01L29/78696

Abstract: The semiconductor device is manufactured by the following method. A first oxide semiconductor film is formed over a first gate electrode and a first insulating film, oxygen is added to the first oxide semiconductor film, and then a second oxide semiconductor film is formed over the first oxide semiconductor film. Then, heat treatment is performed. Next, part of the first insulating film, part of the first oxide semiconductor film, and part of the second oxide semiconductor film are etched to form a first gate insulating film having a projection. Next, a pair of electrodes is formed over the second oxide semiconductor film, and a third oxide semiconductor film is formed over the second oxide semiconductor film and the pair of electrodes. Then, a second gate insulating film is formed over the third oxide semiconductor film, and a second gate electrode is formed over the second gate insulating film.

Abstract translation: 半导体器件通过以下方法制造。 在第一栅电极和第一绝缘膜上形成第一氧化物半导体膜，在第一氧化物半导体膜上添加氧，然后在第一氧化物半导体膜上形成第二氧化物半导体膜。 然后进行热处理。 接下来，蚀刻第一绝缘膜的一部分，第一氧化物半导体膜的一部分和第二氧化物半导体膜的一部分，以形成具有突起的第一栅极绝缘膜。 接着，在第二氧化物半导体膜上形成一对电极，在第二氧化物半导体膜和一对电极上形成第三氧化物半导体膜。 然后，在第三氧化物半导体膜上形成第二栅极绝缘膜，在第二栅极绝缘膜上形成第二栅电极。

公开(公告)号：US09449853B2

公开(公告)日：2016-09-20

申请号：US14471766

申请日：2014-08-28

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yoshitaka Yamamoto ,  Tetsuhiro Tanaka ,  Takayuki Inoue ,  Hideomi Suzawa

IPC: H01L21/336 ,  H01L21/441 ,  H01L21/473 ,  H01L29/786 ,  H01L29/51 ,  H01L21/02 ,  H01L29/66 ,  H01L29/423 ,  H01L21/28 ,  H01L29/792 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/465 ,  H01L29/49 ,  H01L27/12 ,  H01L21/316

CPC classification number: H01L29/7869 ,  H01L21/0214 ,  H01L21/02181 ,  H01L21/02266 ,  H01L21/02274 ,  H01L21/28194 ,  H01L21/28282 ,  H01L21/31116 ,  H01L21/31122 ,  H01L21/31645 ,  H01L21/32136 ,  H01L21/441 ,  H01L21/465 ,  H01L21/473 ,  H01L27/1225 ,  H01L29/24 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/517 ,  H01L29/66969 ,  H01L29/78648 ,  H01L29/78693 ,  H01L29/78696 ,  H01L29/792

Abstract: A semiconductor device in which the threshold is adjusted is provided. In a transistor including a semiconductor, a source or drain electrode electrically connected to the semiconductor, a gate electrode, and an electron trap layer between the gate electrode and the semiconductor, the electron trap layer includes crystallized hafnium oxide. The crystallized hafnium oxide is deposited by a sputtering method using hafnium oxide as a target. When the substrate temperature is Tsub (° C.) and the proportion of oxygen in an atmosphere is P (%) in the sputtering method, P≧45−0.15×Tsub is satisfied. The crystallized hafnium oxide has excellent electron trapping properties. By the trap of an appropriate number of electrons, the threshold of the semiconductor device can be adjusted.

Abstract translation: 提供其中调整阈值的半导体器件。 在包括半导体，与半导体电连接的源电极或漏电极，栅电极和栅电极和半导体之间的电子捕获层的晶体管中，电子捕获层包括结晶的氧化铪。 通过使用氧化铪作为靶的溅射法沉积结晶的氧化铪。 溅射法中，衬底温度为Tsub（℃），气氛中氧的比例为P（％）时，P≥45〜0.15×Tsub。 结晶的氧化铪具有优异的电子捕获性能。 通过适当数量的电子的陷阱，可以调整半导体器件的阈值。

公开(公告)号：US09349418B2

公开(公告)日：2016-05-24

申请号：US14582319

申请日：2014-12-24

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yoshitaka Yamamoto ,  Kiyoshi Kato

IPC: G11C11/00 ,  G11C11/14 ,  G11C5/14 ,  H01L27/108 ,  H01L27/06 ,  H01L29/786 ,  G11C8/16 ,  G11C11/405 ,  G11C11/408 ,  G11C11/56 ,  H01L27/115

CPC classification number: G11C5/14 ,  G11C7/12 ,  G11C8/08 ,  G11C8/10 ,  G11C8/16 ,  G11C11/24 ,  G11C11/405 ,  G11C11/4087 ,  G11C11/409 ,  G11C11/565 ,  G11C2207/108 ,  H01L23/528 ,  H01L27/0688 ,  H01L27/1052 ,  H01L27/10814 ,  H01L27/1082 ,  H01L27/10826 ,  H01L27/10855 ,  H01L27/10858 ,  H01L27/10873 ,  H01L27/10879 ,  H01L27/10897 ,  H01L27/1156 ,  H01L27/1207 ,  H01L27/1225 ,  H01L27/1255 ,  H01L27/1259 ,  H01L29/24 ,  H01L29/786 ,  H01L29/7869

Abstract: A novel semiconductor device where multilevel data can be written and read. The semiconductor device includes first to fifth transistors, a capacitor, a bit line, and a power supply line. Write operation is performed in such a manner that first data is supplied to a gate of the fifth transistor through the first transistor; the first transistor is turned off; second data is supplied to a second electrode of the capacitor through the second transistor to convert the first data into third data; and the second electrode of the capacitor are made electrically floating. The second electrode of the capacitor is initialized to GND through the third transistor. Read operation is performed by charging or discharging the bit line through the fourth transistor and the fifth transistor. The first to third transistors are preferably oxide semiconductor transistors.

Abstract translation: 可以写入和读取多级数据的新型半导体器件。 半导体器件包括第一至第五晶体管，电容器，位线和电源线。 以通过第一晶体管将第一数据提供给第五晶体管的栅极的方式执行写入操作; 第一个晶体管关闭; 第二数据通过第二晶体管提供给电容器的第二电极，以将第一数据转换为第三数据; 并且使电容器的第二电极电浮动。 电容器的第二个电极通过第三个晶体管初始化为GND。 通过对第四晶体管和第五晶体管的位线进行充电或放电来进行读操作。 第一至第三晶体管优选为氧化物半导体晶体管。

公开(公告)号：US20150187775A1

公开(公告)日：2015-07-02

申请号：US14582319

申请日：2014-12-24

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yoshitaka Yamamoto ,  Kiyoshi Kato

IPC: H01L27/108 ,  G11C7/12 ,  G11C5/14 ,  G11C11/419

CPC classification number: G11C5/14 ,  G11C7/12 ,  G11C8/08 ,  G11C8/10 ,  G11C8/16 ,  G11C11/24 ,  G11C11/405 ,  G11C11/4087 ,  G11C11/409 ,  G11C11/565 ,  G11C2207/108 ,  H01L23/528 ,  H01L27/0688 ,  H01L27/1052 ,  H01L27/10814 ,  H01L27/1082 ,  H01L27/10826 ,  H01L27/10855 ,  H01L27/10858 ,  H01L27/10873 ,  H01L27/10879 ,  H01L27/10897 ,  H01L27/1156 ,  H01L27/1207 ,  H01L27/1225 ,  H01L27/1255 ,  H01L27/1259 ,  H01L29/24 ,  H01L29/786 ,  H01L29/7869

Abstract: A novel semiconductor device where multilevel data can be written and read. The semiconductor device includes first to fifth transistors, a capacitor, a bit line, and a power supply line. Write operation is performed in such a manner that first data is supplied to a gate of the fifth transistor through the first transistor; the first transistor is turned off; second data is supplied to a second electrode of the capacitor through the second transistor to convert the first data into third data; and the second electrode of the capacitor are made electrically floating. The second electrode of the capacitor is initialized to GND through the third transistor. Read operation is performed by charging or discharging the bit line through the fourth transistor and the fifth transistor. The first to third transistors are preferably oxide semiconductor transistors.

Abstract translation: 可以写入和读取多级数据的新型半导体器件。 半导体器件包括第一至第五晶体管，电容器，位线和电源线。 以通过第一晶体管将第一数据提供给第五晶体管的栅极的方式执行写入操作; 第一个晶体管关闭; 第二数据通过第二晶体管提供给电容器的第二电极，以将第一数据转换为第三数据; 并且使电容器的第二电极电浮动。 电容器的第二个电极通过第三个晶体管初始化为GND。 通过对第四晶体管和第五晶体管的位线进行充电或放电来进行读操作。 第一至第三晶体管优选为氧化物半导体晶体管。